ASIC Engineer for Satellite Network (Project Leo)

Amazon; Redmond (WA); On-site; USD 110,000 - 160,000; Full time

Job summary

Amazon Leo is seeking an ASIC Engineer to join a cross-disciplinary team in Redmond, WA, to design, verify, and optimize custom silicon. You will engage with senior engineers to drive concept through production, gaining exposure to the full design lifecycle.

You will work on logic design, verification, and post-silicon validation, collaborating with physical design teams to meet performance and area goals. A Bachelor's in EE/CE and experience with C/C++ and SystemVerilog are preferred.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related fields.
• Experience troubleshooting and debugging technical systems with strong analytical skills and effective communication.
• Experience in RTL coding and debug, performance/power/area analysis, and trade-offs.
• Experience in C/C++ and SystemVerilog coding.
• Experience with physical design teams to develop highly optimized ASICs.
• Experience with modern ASIC/FPGA design and verification tools.

Responsibilities

• Participate in logic design, verification and post-silicon validation as part of Amazon custom silicon solutions.
• Work with physical design teams to achieve performance and area requirements.
• Develop a deep understanding of end customer requirements, including software applications, use models, system architecture and the SoC architecture.
• Develop and execute design automation mechanisms and flows.

Skills

C/C++

RTL coding

SystemVerilog

ASIC/FPGA design

Verification tools

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, or related fields

Tools

Verilog

ASIC/FPGA design tools

Job description

Amazon Leo is seeking an ASIC Engineer to join a cross-disciplinary team in Redmond, WA, to design, verify, and optimize custom silicon. You will engage with senior engineers to drive concept through production, gaining exposure to the full design lifecycle.

You will work on logic design, verification, and post-silicon validation, collaborating with physical design teams to meet performance and area goals. A Bachelor's in EE/CE and experience with C/C++ and SystemVerilog are preferred.