ASIC Chip Lead

W3Global; Brooklyn Park (MN); On-site; USD 145,000 - 205,000; Full time

Benefits offered by this job

Health insurance

Dental insurance

401K with profit sharing

PTO

Stock options

Job summary

W3Global is seeking an experienced ASIC Chip Lead and Design Engineer to drive the development of custom ASICs in a high-performance environment. You will oversee the full design lifecycle, from concept to implementation, collaborating with cross-functional teams to meet stringent performance, power, and area targets.

The ideal candidate has hands-on experience with complex digital blocks, radiation-hardened design, analog/mixed-signal design, and EDA toolchains.

Qualifications

• 10+ years of direct industry experience with ASIC/SoC design.
• Proficiency in RTL based digital IC design using Verilog/SystemVerilog.
• Strong knowledge of EDA tools and RTL optimization.

Responsibilities

• Lead architectural design of ASICs based on high-level requirements.
• Define chip functionality, interfaces and performance targets with system architects.
• Develop detailed specifications for chip components and ensure timely delivery.

Skills

ASIC/SoC design

RTL Verilog/SystemVerilog

EDA tools

UNIX/Linux scripting

C/C++ programming

Mentoring

Education

Bachelor's or Master's in EE/CS

Tools

Synopsys Design Compiler

Job description

Company Description

Our client provides integrated circuit development services from concept to qualified part delivery leveraging the best-in-class on-shore manufacturing capabilities. Our client specializes in IC design and high-density package solutions with expertise in radiation hardening for space and strategic applications. Our client is a Trusted accredited supplier and a non-traditional defense contractor.

About The Job

Company Description

Our client provides integrated circuit development services from concept to qualified part delivery leveraging the best-in-class on-shore manufacturing capabilities. Our client specializes in IC design and high-density package solutions with expertise in radiation hardening for space and strategic applications. Our client is a Trusted accredited supplier and a non-traditional defense contractor.

Our client has an immediate opening for an experienced ASIC Chip Lead and Design Engineer.

Job Description

As an ASIC Chip Lead and Design Engineer, you will play a pivotal role in the development of custom-designed Application-Specific Integrated Circuits (ASICs). Your expertise will span the entire chip design lifecycle, from conceptualization to implementation. You'll collaborate with cross-functional teams, ensuring successful chip development while adhering to performance, power, and area targets. The right candidate will be someone with high aptitude who is currently hands on designing complex digital blocks, with strong knowledge/experience across the complete ASIC/SOC design flow. An ideal candidate will additionally have experience with radiation-hardened design, analog/mixed-signal design and EDA, and std-cell library development.

Additional duties include the evaluation of customer requirements and estimates of effort/expenses for potential new business, and participation in identifying problems with and improvements to, internal design methodologies.

Essential Duties And Qualifications

Chip Architecture and Development:

• Lead the architectural design of ASICs based on high-level requirements and block diagrams.
• Collaborate with system architects to define chip functionality, interfaces, and performance targets.
• Develop detailed specifications for the chip's components.

RTL Design And Synthesis

• Use Synopsys Design Compiler to create RTL (Register Transfer Level) designs.
• Optimize RTL code for area, power, and performance.
• Implement and verify complex digital blocks.

Constraint Development

• Develop timing constraints for the entire chip.
• Work closely with physical design teams to ensure successful place-and-route.

RISC Processor Conformance

• Constrain and verify RISC processors within the chip.
• Optimize processor performance and power efficiency.

Physical Design Collaboration

• Collaborate with physical design teams on floorplanning, placement, and routing.
• Address any design closure issues.

Verification Support

• Work with verification engineers to ensure functional correctness.
• Assist in creating testbenches and verifying the chip's functionality.

Modern revision-control tools and best-practices in a collaborative, multi-site design community.

Proficiency with UNIX/Linux incl. shell scripting, text utilities (e.g. sed, awk, grep), using Modules, high-level programming such as C/C++, PERL/Python/TCL scripting.

Proficiency with Windows apps, incl. Word, Excel, PowerPoint, Visio, Project, PDF conversion.

Qualifications

• Bachelors/master's in electrical engineering/computer science or equivalent.
• 10+ years of direct industry experience with ASIC and/or SoC design.
• Proficiency in Synopsys Design Compiler and other EDA tools.
• Strong understanding of digital design principles.
• Familiarity with RISC architectures (e.g., ARM, MIPS).
• Excellent problem-solving skills and attention to detail.
• A strong background in RTL based digital IC design using Verilog/SystemVerilog
• Proven track record of first-pass successes.
• A self-starter with the ability to assume leadership roles.
• Ability to work well in a diverse team environment.
• Willingness to Mentor less senior engineers.
• Experience with industry standard development tools and methodologies.

Base Salary: $145,000-$205,000.

Location: Work on-site at the Brooklyn Park, MN.

Benefits: Health insurance, Dental insurance, 401K Plan with profit sharing, Paid Time Off (PTO), Stock option plan