Senior Embedded CPU Power & Performance Architect

Socket.dev; Santa Clara (CA); Hybrid; USD 210,000 - 310,000; Full time

Job summary

AMD in Santa Clara is seeking a lead PPA Architect to ensure CPU Core & Cache complexes in embedded products meet performance while managing reliability, power delivery, and thermal constraints. This is a technical leadership role linking CPU IP definition with the Embedded BU’s usage model and operating conditions.

You will drive cross‑functional alignment with architecture, physical design implementation, FW/BIOS, SIPI, and platform teams, owning end-to-end workstreams and closing risks and

Qualifications

• BS/MS in EE/CE (or equivalent) with 7–10 years of relevant experience.
• Proven cross-functional leadership across architecture, design, FW/BIOS, SIPI, and platform teams.
• Strong understanding of SoC architecture, PDN, and thermal management.
• Experience delivering review-ready technical workstreams and managing risks.

Responsibilities

• Align Product Requirements with Cores IP and the usage model.
• Lead power delivery, packaging, and platform definition decisions.
• Lead thermal modeling and packaging to meet margins.
• Translate usage models into IP performance, power, and thermal constraints.
• Collaborate across Embedded BU and CPU design teams to align roadmaps.
• Drive technical reviews across SoC architecture, physical design, and packaging.

Skills

Cross-functional leadership

SoC architecture

Power delivery

Thermal management

Reliability engineering

Pre-silicon modeling

Program milestone readiness

FW/BIOS validation

Education

BS/MS in EE/CE

Job description

AMD in Santa Clara is seeking a lead PPA Architect to ensure CPU Core & Cache complexes in embedded products meet performance while managing reliability, power delivery, and thermal constraints. This is a technical leadership role linking CPU IP definition with the Embedded BU’s usage model and operating conditions.

You will drive cross‑functional alignment with architecture, physical design implementation, FW/BIOS, SIPI, and platform teams, owning end-to-end workstreams and closing risks and