Analog Layout Engineer

Hays; California (MO); On-site; USD 100,000 - 150,000; Full time

Job summary

A leading company is seeking an Analog Layout Engineer with expertise in high-speed, complex IC layouts. Candidates should have extensive experience in analog and RF layout, advanced CMOS FinFET technologies, and industry-standard EDA tools. This contract role includes comprehensive benefits and a focus on inclusivity and diversity within the workplace.

Benefits

Medical benefits

Dental benefits

Vision benefits

401K

Life Insurance

Qualifications

• Minimum 7+ years of experience in Analog and RF layout.
• Experience developing and leading complex IC layouts for high-speed applications.
• Knowledge of layout techniques including floor planning and thermal-aware layout.

Responsibilities

• Develop complex IC layouts for high-speed applications.
• Lead layout for high-performance analog mixed-signal blocks.
• Conduct floor planning and top-level chip assembly.

Skills

Analog layout

RF layout

High-speed applications

Complex IC layouts

CMOS FinFET technologies

EDA tools

High-performance blocks

Thermal-aware layout

Electro-migration considerations

Tools

Synopsys

Cadence

Mentor

Python

Job description

The final salary or hourly wage for this position depends on various factors, including qualifications, skills, experience, and geographic location.

Applicants must be legally authorized to work in the United States. Sponsorship is not available.

Our client is seeking an Analog Layout Engineer in Santa Clara, CA.

Skills & Requirements

• Minimum 7+ years of experience in Analog and RF layout.
• Experience developing and leading complex IC layouts for high-speed applications in advanced CMOS FinFET technologies (7nm, 3nm) at block and chip levels.
• Knowledge of complex layout ICs for ultra-low power applications using advanced CMOS FinFET technologies for ASIC/SOC designs.
• Thorough knowledge of industry-standard EDA tools from Cadence, Mentor, and Synopsys.
• Experience with layout of high-performance, high-speed analog mixed-signal blocks such as TIAs, CMOS drivers, high-speed data converters, and PLLs.
• Experience with floor planning, block-level routing, and top-level chip assembly.
• Knowledge of layout techniques including floor planning, layer generation, thermal-aware layout, and electro-migration considerations.

Preferred Skills

• Synopsys/Cadence/Mentor Layout tools (Preference: 5)
• Python (Preference: 3)
• TSMC 7nm or 5nm (Preference: 3)
• TSMC 3nm (Preference: 5)

Benefits/Other Compensation

This is a contract/temporary role with full medical, dental, vision benefits, 401K, and Life Insurance ($20,000 benefit).

Why Hays?

Work with a knowledgeable recruiter who guides you through screening, resume writing, interview tips, and career planning. Support is provided to help you succeed in your job search.

Additional Information

Hays promotes diversity and equal employment opportunity, adhering to all applicable laws. We are committed to inclusivity and reasonable accommodations for individuals with disabilities. Contact us at 813.336.5570 for accommodations or questions.

Drug testing may be required. Contact a recruiter for more details.

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