Enable job alerts via email!

Senior Analog Layout Engineer

Capgemini

California (MO)

On-site

USD 90,000 - 150,000

Full time

30+ days ago

Boost your interview chances

Create a job specific, tailored resume for higher success rate.

Job summary

An established industry player is seeking a Senior Analog Layout Engineer to lead the design of high-performance analog cores. This role requires extensive experience in IC layout using advanced CMOS processes, particularly in 3nm and 5nm nodes. You will be responsible for utilizing industry-standard EDA tools to create and verify layouts, ensuring adherence to best practices. Join a dynamic team that values innovation and supports your professional growth with flexible work options and comprehensive well-being programs. This is your chance to make a significant impact in a leading engineering firm while enjoying a supportive work environment.

Benefits

Flexible work
Healthcare including dental and vision
401(k) and Employee Share Ownership Plan
Paid time off and holidays
Paid parental leave
Adoption assistance
Subsidized child/elder care
Mentoring and coaching programs

Qualifications

  • 10+ years in high-performance analog layout with advanced CMOS process.
  • Experience with layout of analog blocks like ADCs and PLLs.

Responsibilities

  • Design analog layout using EDA tools for silicon chip production.
  • Set up LVS, DRC, ERC environments and debug verification issues.

Skills

High performance analog layout
CMOS process experience
IC layout design
TSMC FinFET process
Layout automation
Strong communication skills

Education

Bachelor of Science in Electrical Engineering
Equivalent degree in Electronic Communication

Tools

Cadence
Mentor
Synopsys

Job description

Senior Analog Layout Engineer will be responsible for layout of high-performance analog cores such as analog-to-digital converters, digital-to-analog converters, PLL, transceivers, etc.
Responsibilities include leading IC layout of cutting-edge high-performance, high-speed CMOS integrated circuits in foundry CMOS process nodes in 3nm, 5nm, 7nm, 16nm, following best practices from the industry.

Key responsibilities:
  • Designing analog layout using industry standard EDA tools from Cadence, Mentor and Synopsys for silicon chip design and production.
  • Setting up LVS, DRC, ERC environments and debugging verification issues using Cadence and Mentor tools.
  • Working extensively with RF, Serdes, Analog blocks and Transceiver; also working with floor planning, block level routing and top-level chip assembly.
  • Applying knowledge of high-performance analog layout techniques such as common centroid layout, shielding, use of dummy devices, thermal aware layout with consideration for electromigration.
Required Skills
  • 10+ years’ experience in high performance analog layout in advanced CMOS process.
  • Experience in IC layout of cutting-edge high-performance, high-speed CMOS integrated circuits in foundry CMOS process nodes in 3nm, 5nm.
  • Experience with layout of high-performance analog blocks such as analog to digital converters, references, digital to analog converters, PLL etc. desired.
  • Excellent hands-on experience with TSMC FinFET process 3nm, 5nm and 7nm nodes. Experience working with distributed design teams.
  • Knowledge of skill code and layout automation.
  • Self-starter with the ability to define and adhere to a schedule. Must possess strong written and verbal communication skills.
  • Education background – Bachelor of Science or Electrical Engineering or Electronic communication or equivalent.

Life at Capgemini

Capgemini supports all aspects of your well-being throughout the changing stages of your life and career. For eligible employees, we offer:

  • Flexible work
  • Healthcare including dental, vision, mental health, and well-being programs
  • Financial well-being programs such as 401(k) and Employee Share Ownership Plan
  • Paid time off and paid holidays
  • Paid parental leave
  • Family building benefits like adoption assistance, surrogacy, and cryopreservation
  • Social well-being benefits like subsidized back-up child/elder care and tutoring
  • Mentoring, coaching and learning programs
  • Employee Resource Groups
  • Disaster Relief
About Capgemini Engineering

World leader in engineering and R&D services, Capgemini Engineering combines its broad industry knowledge and cutting-edge technologies in digital and software to support the convergence of the physical and digital worlds. Coupled with the capabilities of the rest of the Group, it helps clients to accelerate their journey towards Intelligent Industry.

Capgemini is an Equal Opportunity Employer encouraging diversity in the workplace. All qualified applicants will receive consideration for employment without regard to race, national origin, gender identity/expression, age, religion, disability, sexual orientation, genetics, veteran status, marital status or any other characteristic protected by law.

This is a general description of the Duties, Responsibilities and Qualifications required for this position. Physical, mental, sensory or environmental demands may be referenced in an attempt to communicate the manner in which this position traditionally is performed.

Get your free, confidential resume review.
or drag and drop a PDF, DOC, DOCX, ODT, or PAGES file up to 5MB.

Similar jobs

Senior Analog Layout Engineer

Capgemini Engineering

California

On-site

USD 124,000 - 188,000

15 days ago

Senior Analog Layout Engineer

Capgemini

California

On-site

USD 88,000 - 167,000

17 days ago

Senior Analog Layout Engineer

Capgemini

California

On-site

USD 88,000 - 167,000

17 days ago

Senior Analog Layout Engineer

Capgemini

California

On-site

USD 124,000 - 188,000

17 days ago

Senior Analog Layout Engineer

Capgemini

California

On-site

USD 76,000 - 179,000

30+ days ago

Senior Analog Layout Engineer

Marvell Semiconductor, Inc.

California

On-site

USD 84,000 - 128,000

30+ days ago

Senior Engineer, Analog Layout

Marvell Semiconductor, Inc.

California

On-site

USD 84,000 - 128,000

30+ days ago