Analog layout design,Staff Engineer

Synopsys, Inc.; Sunnyvale (CA); On-site; USD 90,000 - 150,000; Full time

Job summary

Join a forward-thinking company as an Analog Layout Design Engineer, where your expertise will drive innovation in semiconductor technology. In this dynamic role, you'll be hands-on in developing high-quality layouts for cutting-edge DDR/HBM/UCIe IPs. Collaborate with a passionate team, solve complex challenges, and contribute to the success of next-generation silicon solutions. This role offers an exciting opportunity to enhance performance and reliability while fostering an inclusive environment that values diverse perspectives. If you're ready to make a significant impact in the tech industry, this is the perfect opportunity for you.

Qualifications

• 4+ years of experience in analog layout design with a proven track record.
• Strong understanding of deep submicron effects and verification timelines.

Responsibilities

• Develop layouts for next-gen DDR/HBM/UCIe IPs while ensuring compliance.
• Solve complex problems and debug issues effectively.

Skills

Analog Layout Design

Problem-Solving

Collaboration

Communication Skills

Detail Orientation

Education

BTech/MTech in relevant field

Tools

DRC

LVS

ERC

CMOS

FinFET

GAA process technologies

Job description

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a passionate and skilled Analog Layout Design Engineer with a keen eye for detail and a deep understanding of advanced semiconductor technologies. You thrive in dynamic environments and possess a strong problem-solving aptitude. With a profound expertise in developing high-quality layouts and physical verification techniques, you are ready to contribute to cutting-edge DDR/HBM/UCIe IP development. You excel in collaboration, fostering accountability and ownership within teams, and have excellent written, verbal communication, and interpersonal skills. Your commitment to diversity and inclusion aligns with Synopsys’ values, and you are eager to work in an environment that welcomes all perspectives.

What You’ll Be Doing:

• Hands-on development of layout for next-generation DDR/HBM/UCIe IPs.
• Solving complex problems and debugging issues effectively.
• Executing layout floorplanning, routing, and physical verifications to meet stringent quality requirements.
• Ensuring compliance with DRC, LVS, ERC, and antenna rules.
• Applying deep submicron effects, floorplan techniques in CMOS, FinFET, and GAA process technologies (7nm and below).
• Implementing layout matching techniques, ESD, latch-up, EMIR, DFM, and LEF generation.

The Impact You Will Have:

• Enhancing the performance and reliability of Synopsys’ DDR/HBM/UCIe IPs.
• Accelerating the integration of advanced capabilities into SoCs.
• Reducing risk and improving time-to-market for differentiated products.
• Driving innovation in semiconductor technology and design.
• Contributing to the success of Synopsys’ Silicon IP business.
• Fostering a collaborative and inclusive work environment.

What You’ll Need:

• BTech/MTech degree in a relevant field.
• 4+ years of experience in analog layout design.
• Proven track record in developing high-quality layouts and meeting verification timelines.
• Strong understanding of deep submicron effects and floorplan techniques.
• Exposure to layout matching, ESD, latch-up, EMIR, DFM, and LEF generation.

Who You Are:

• Detail-oriented with excellent problem-solving skills.
• Collaborative and able to foster accountability and ownership.
• Strong written, verbal communication, and interpersonal skills.
• Committed to diversity and inclusion.

The Team You’ll Be A Part Of:

You will be part of a dynamic team focused on developing next-generation DDR/HBM/UCIe PHY IPs. Our team values innovation, collaboration, and continuous improvement, driving the success of Synopsys’ Silicon IP business.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.