Silicon Verification Engineer 1

HireTalent; Mountain View (CA); Remote; USD 90,000 - 120,000; Full time

Job summary

A leading company is seeking a Silicon Verification Engineer to join their team in Mountain View, CA. The role involves defining and implementing verification plans, working with design teams, and ensuring high-quality verification of SOC chip designs. Ideal candidates will have experience with SystemVerilog and UVM, along with a strong background in mixed signal verification. This position offers opportunities for growth and contribution to cutting-edge projects in AI and computing.

Qualifications

• 2+ years experience with SystemVerilog and UVM.
• Experience with Mixed Signal Verification.
• Experience with Design Verification Methodology.

Responsibilities

• Define and implement a UVM verification environment.
• Write and implement test plans.
• Support post-silicon verification activities.

Skills

SystemVerilog

UVM

Mixed Signal Verification

Design Verification Methodology

Effective communication

Collaboration

Teamwork

Education

Bachelor’s degree in Electrical Engineering

Bachelor’s degree in Computer Engineering

Bachelor’s degree in Computer Science

Job description

Job Title: Silicon Verification Engineer 1
Job Location: Mountain View, CA (Remote)
Job Duration: 03+ months on W2 (High chances of Extension)

Summary:
The main function of Silicon Verification Engineer is to be a part of the test-plan generation process, creating, testing, and implementing various verification plans.

Job Responsibilities:
• Define, document, and implement a UVM verification environment including agents and scoreboards
• Write test plans and implement them by developing tests, test generators, test benches, checkers, coverage, and other verification collateral
• Run tests on RTL and Gate Level Netlists, debug failures to root cause, and recommend fixes
• Support post-silicon verification activities of the products working with design and product teams

Candidate Requirements
• Years of Experience Required: 2+ (ideally 3-6) overall years of experience in the field.
• Degrees or certifications required: Not required but nice to have.
• Disqualifiers: Candidates must have a strong grasp of SystemVerilog and UVM. If they only have IT experience and are not familiar with VMM/ OVM/ UVM they will not be eligible for the role.
• Best vs. Average: The ideal resume would contain previous experience with mixed signal exposure (analog and digital), and is fluent with SystemVerilog and UVM having significant design verification experience.
• Performance Indicators: Performance will be assessed based on completion of tasks within deadlines, and responding to team questions and communicating issues with the team in a quick and timely manner.

Education/Experience:
• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related degree required
•0-2 years of relevant experience required.:
• Purpose of the Team: The purpose of this team is IP verification to verify the design of high speed interface connecting different parts of an SOC chip.
• Key projects: This role will contribute to internal projects that cannot be shared at the moment. They will be working on Certus interfaces and high-speed serial interfaces (CRDAS) for several projects in AI and compute.
• Typical task breakdown and operating rhythm: The role will consist of meetings every day in the mornings which will go over agenda items like tasks and important actions. The remainder of their time is spent heads down focusing on assigned tasks (coding, data analysis, task management).

Skills:
• Proficient in using Verilog and VMM/OVM/UVM
• Experience in pre and post silicon verification test flow and automated test benches
• Effective communication, collaboration, and teamwork skills


Top 3 Hard Skills Required + Years of Experience
1. Minimum 2+years experience with SystemVerilog and UVM.
2. Minimum 2+years experience with Mixed Signal Verification.
3. Minimum 2+years experience with Design Verification Methodology.