Analog IC Layout Engineer

NeuroTechX

South San Francisco (CA)

On-site

USD 83,000 - 139,000

Full time

38 hours ago
Be an early applicant
Application generator

An application made for this job — a tailored resume and cover letter that speak straight to the posting.

Get past ATS filters

Benefits offered by this job

Medical insurance
Paid holidays
Commuter benefits
Meals provided
Equity (RSUs)
401(k) plan
Parental leave
Flexible time off

Job summary

Neuralink in the United States is seeking an Analog IC Layout Engineer to craft layouts for mixed-signal and analog circuits and work with chip designers and engineers on a small, agile team.

You will design amplifiers, filters, data converters, and power management circuits, leveraging 2+ years in analog/mixed-signal layout and FinFET experience, with equity RSUs offered for all full-time employees.

Qualifications

  • 2+ years of experience in analog and mixed-signal IC layout design.
  • 1+ year experience with FinFET technologies.
  • Ability to identify best approach to solving problems.

Responsibilities

  • Craft state-of-the-art layouts for mixed-signal and analog circuits.
  • Review layout floorplans and analyze high-fidelity circuits with engineers.
  • Physically verify custom IC mask layouts (LVS, DRC, ERC).

Skills

Analog layout
FinFET experience
Problem solving

Tools

SKILL
TCL
Shell
C/C++
Python

Job description

About Neuralink

We are creating devices that enable a bi-directional interface with the brain. These devices allow us to restore movement to the paralyzed, restore sight to the blind, and revolutionize how humans interact with their digital world.

Team Description

The Brain Interfaces SOC Department delivers chip architecture and silicon implementation of neural recording and stimulation system-on-chip (SoC) for high-bandwidth brain-computer interfaces. We have crafted a team of exceptional engineers whose mission is to push the frontiers of what is possible today and define the future.

Job Description And Responsibilities

We are looking for experienced and hands-on engineers with a creative and initiative mindset, who are interested in exploring the next-generation chip design with advanced architectures and hardware accelerators with a goal of enhancing the energy efficiency, information entropy, and scalability of our wireless brain-computer interfaces towards the physical limit of silicon technology. The ideal candidates are energetic people who get excited about building things, are highly analytical, and enjoy tackling new problems. You will have the opportunity to collaborate closely with chip designers, electrical engineers, algorithms engineers, and software engineers on a small, agile team. As an Analog IC Layout Engineer, your responsibilities will include:

  • Crafting state-of-the-art layouts for mixed-signal and analog circuits
    • Amplifiers
    • Filters
    • Switched capacitor circuits
    • Oscillators
    • Data converters
    • Power management circuits
  • Reviewing layout floorplans and analyzing high-fidelity circuits with circuit engineers
  • Physical verification of custom IC mask layouts (LVS, DRC, ERC)
Required Qualifications
  • 2+ years of experience in analog and mixed-signal IC layout design
  • 1+ year experience with FinFET technologies
  • Ability to identify the best approach to solving problems
Preferred Qualifications
  • Programming/scripting knowledge in SKILL, TCL, Shell, C/C++, and/or Python
  • Proven expertise in implementing analog and mixed-signal layout designs, achieving tight matching, low noise, and low power consumption
  • Understanding on failure-prone circuit and layout structures
  • Experience with analog DFM standards
  • Experience with layout P-cell design and implementation
  • Experience with layout automation
Expected Compensation

The anticipated base salary for this position is expected to be within the following range. Your actual base pay will be determined by your job-related skills, experience, and relevant education or training. We also believe in aligning our employees’ success with the company’s long-term growth. As such, in addition to base salary, Neuralink offers equity compensation (in the form of Restricted Stock Units (RSU)) for all full-time employees.

Base Salary Range

$83,000-$139,000 USD

What We Offer
  • An opportunity to change the world and work with some of the smartest and most talented experts from different fields
  • Growth potential; we rapidly advance team members who have an outsized impact
  • Excellent medical, dental, and vision insurance through a PPO plan
  • Paid holidays
  • Commuter benefits
  • Meals provided
  • Equity (RSUs) *Temporary Employees & Interns excluded
  • 401(k) plan *Interns initially excluded until they work 1,000 hours
  • Parental leave *Temporary Employees & Interns excluded
  • Flexible time off *Temporary Employees & Interns excluded
Get your free, confidential resume review.
or drag and drop your file here.
Similar jobs

Similar jobs worth comparing

Analog IC Design and Verification Engineer
Analog IC Design and Verification Engineer

Future Ventures • California (MO)

On-site
USD 125,000 - 291,000
Excellent medical, dental, and vision
Equity (RSUs)
Paid holidays
+3
Analog IC Design and Verification Engineer
Analog IC Design and Verification Engineer

NeuroTechX • South San Francisco (CA)

On-site
USD 125,000 - 291,000
Medical insurance
Dental insurance
Vision insurance
+7
Analog IC Design and Verification Engineer
Analog IC Design and Verification Engineer

Neuralink • South San Francisco (CA)

On-site
USD 125,000 - 291,000
Equity (RSUs)
Medical, dental, vision insurance
401(k) plan
Analog and Mixed-Signal IC Design Engineer Intern
Analog and Mixed-Signal IC Design Engineer Intern

NeuroTechX • South San Francisco (CA)

On-site
USD 40,000 - 57,000
Excellent medical, dental, and vision
Paid holidays
Commuter benefits
+5
Digital IC Design Engineer
Digital IC Design Engineer

NeuroTechX • South San Francisco (CA)

On-site
USD 116,000 - 234,000
Medical, dental, and vision insurance
Equity (RSUs)
401(k) plan
+5
Software Engineer, ASIC
Software Engineer, ASIC

Latent AI • South San Francisco (CA)

On-site
USD 123,000 - 216,000
Medical, dental, and vision insurance
401(k) plan
Flexible time off
Hardware/ Software Co-Design Engineer
Hardware/ Software Co-Design Engineer

Future Ventures • Austin (TX)

On-site
USD 151,000 - 261,000
Excellent medical, dental, and vision insurance
Paid holidays
Commuter benefits
+5
Electrical Engineer, Implant Embedded Systems
Electrical Engineer, Implant Embedded Systems

NeuroTechX • South San Francisco (CA)

On-site
USD 110,000 - 238,000
Equity (RSUs)
401(k) plan
Parental leave
+4
Hardware/ Software Co-Design Engineer
Hardware/ Software Co-Design Engineer

Future Ventures • Austin (TX)

On-site
USD 151,000 - 261,000
Excellent medical, dental, and vision insurance
Paid holidays
Commuter benefits
+5
Electrical Engineer, Implant Embedded Systems
Electrical Engineer, Implant Embedded Systems

Neuralink • San Francisco (CA)

On-site
USD 109,000 - 239,000
Medical, dental, and vision insurance
401(k) plan
Equity compensation
+4