Hardware/ Software Co-Design Engineer

Roboticsconnected; Austin (TX); In loco; USD 151.000 - 261.000; Tempo pieno

Vantaggi offerti da questo lavoro

Equity (RSUs)

401(k) plan

Medical insurance

Dental insurance

Vision insurance

Paid holidays

Commuter benefits

Meals provided

Parental leave

Flexible time off

Descrizione del lavoro

Neuralink is seeking a Hardware/Software Co-Design Engineer to deliver micro-architecture and RTL for high-throughput, low-power DSPs and accelerators in brain-machine interfaces. You will work with firmware teams to optimize hardware/software interfaces and drive architecture trade-offs across process technology and workload types.

The role requires strong SystemVerilog, C/C++, Python skills, and a track record in RTL design, emulation, and DSP pipelines from algorithm to implementation.

Competenze

• Bachelor degree or equivalent experience in electrical engineering, computer science, or related field.
• Evidence of exceptional ability in EE/CS/CE.
• Experience designing embedded software in C or Rust.
• Expertise in SystemVerilog, C/C++, Python.
• Experience emulation models, transactors, and test environments for hardware behavior.
• Experience in complex digital systems from architecture to RTL.
• Experience designing DSP pipelines from algorithm to RTL.

Mansioni

• Deliver micro-architecture and RTL implementations of low-power DSPs, accelerators, GPUs, and PHY/MAC for brain-machine interfaces.
• Design and optimize hardware/software interface with firmware engineers.
• Perform architecture optimization balancing energy, performance, and cost under process variation.
• Collaborate on silicon bring-up tests with verification teams.

Conoscenze

SystemVerilog

C/C++

Python

Rust

Formazione

B.S. in Electrical Engineering / Computer Science

Descrizione del lavoro

About Neuralink:

We are creating devices that enable a bi-directional interface with the brain. These devices allow us to restore movement to the paralyzed, restore sight to the blind, and revolutionize how humans interact with their digital world.

Team Description:

The Brain Interfaces Soc Department delivers chip architecture and silicon implementation of neural recording and stimulation system-on-chip (SoC) for high-bandwidth brain-machine interface applications. We have crafted a team of exceptional engineers whose mission is to push the frontiers of what is possible today and define the future.

Job Description & Responsibilities:

Our Hardware/ Software Co-Design Engineer will be responsible for delivering micro-architecture and register-transfer level (RTL) implementation of digital IPs and systems with a focus in high-throughput low-power digital signal processor (DSP) and general-purpose hardware accelerators towards realizing state-of-the-art brain-computer interfaces. Relevant product development experience in micro-architecture design for low-power processors, on-chip bus and network interfaces, audio/video compression processors, AI/ML accelerators, and communication PHY/MAC will be preferred.

• Micro-architecture design and RTL implementation of:
  • Low-power digital signal processors
  • Low-power general-purpose hardware accelerators
  • Low-power graphics processing units
  • Low-power radio MAC/PHY
  • Low-power serial link MAC/PHY
• Design and optimization of hardware/software interface with firmware engineers
• Application-specific architecture optimization including:
  • Complex system modeling for energy and performance benchmarks
  • Workload analysis and modeling
  • Energy/performance profiling and analysis
  • Leveraging architecture-level design trade-offs with process technology and workload type
  • Balancing cost and performance under manufacturing process variation
• Collaboration on silicon bring-up tests with verification engineers

Required Qualifications:

• Bachelor of Science (B.S.) degree in Electrical Engineering and/or Computer Science or a related field, or equivalent experience
• Evidence of exceptional ability in electrical engineering, computer science, or computer engineering
• Experience designing and implementing embedded software in C or Rust
• Expertise in SystemVerilog, C/C++, Python
• Experience designing and implementing emulation models, transactors, and test environments to replicate hardware behavior
• Experience working on complex digital systems from architecture, microarchitecture, and RTL, using industry standard tools
• Experience in designing digital signal processing pipelines, from algorithm to RTL

Preferred Qualifications:

• Experience in architecture optimization with process technology customization
• Experience in the verification of complex digital systems, using industry standard tools
• Experience in the physical design of complex digital systems, using industry standard tools
• Experience testing and debugging digital system-on-a-chips
• Functional modeling experience and logic verification with SystemVerilog, SystemC/C++
• Experience automating tool flows
• Experience in processor instruction set architecture design
• Experience in compiler back-end design and customization

Expected Compensation:

The anticipated base salary for this position is expected to be within the following range. Your actual base pay will be determined by your job-related skills, experience, and relevant education or training. We also believe in aligning our employees’ success with the company's long-term growth. As such, in addition to base salary, Neuralink offers equity compensation (in the form of Restricted Stock Units (RSU)) for all full-time employees.

Base Salary Range:

$151,000—$261,000 USD

What We Offer:

Full-time employees are eligible for the following benefits listed below.

• An opportunity to change the world and work with some of the smartest and most talented experts from different fields
• Growth potential; we rapidly advance team members who have an outsized impact
• Excellent medical, dental, and vision insurance through a PPO plan
• Paid holidays
• Commuter benefits
• Meals provided
• Equity (RSUs) *Temporary Employees & Interns excluded
• 401(k) plan *Interns initially excluded until they work 1,000 hours
• Parental leave *Temporary Employees & Interns excluded
• Flexible time off *Temporary Employees & Interns excluded