Analog Design Intern: Mixed-Signal R&D & Verification

Infineon Technologies AG; Austin (TX); On-site; USD 29,000 - 50,000; Full time

Job summary

Infineon Technologies AG in Austin, TX invites students and recent graduates to join WeAreIn in design and verification roles. You will assist with analog and digital design, develop testbenches, verify power management circuits, and perform silicon evaluation using Cadence tools. Strong Python, SystemVerilog, UVM, and Cadence experience are valued.

Collaboration across analog and digital teams is key. This entry-level role offers real projects, hands-on learning, and a pathway to future IP

Qualifications

• Education: Currently enrolled in or recently graduated from a Bachelor's or Master's program in Electrical Engineering or a closely related field
• Cadence Proficiency: Hands-on experience with Cadence tools for schematic creation, netlist generation, and simulation execution in analog or mixed-signal environments
• Verification Languages: Familiarity with hardware verification languages including System Verilog and UVM for constrained random testbench development
• Lab Experience: Exposure to lab test equipment such as oscilloscopes and digital multimeters for hardware bring-up and IC characterization activities
• Programming Skills: Experience with Python programming and Unix/Linux shell commands for scripting, automation, and simulation workflow support
• Protocol Knowledge: Awareness of communication protocols such as PMBus, I2C, UART, or SPI relevant to microcontroller-based testbench and firmware co-verification
• Collaboration Skills: Strong written and verbal communication skills with the ability to contribute effectively within cross-functional engineering teams

Responsibilities

• Assist with analog and digital design and verification of mixed-signal IP using Cadence tools across various SoC scenarios
• Create mixed-signal testbenches and execute simulations for digital multiphase buck controllers, integrated power stages, and voltage regulator designs
• Perform functional verification of power management circuits including digital multiphase buck controllers and integrated power stages
• Conduct bench-level silicon evaluation to characterize IC performance, document results, and prepare structured validation reports
• Develop scalable and reusable constrained random testbenches using System Verilog and UVM object-oriented methodologies
• Partner with analog and digital IC design experts and cross-functional teams to improve unit architecture performance and next-generation IP development
• Build analog and mixed-signal design competencies by actively contributing to next-generation IP and exploring best-in-class product design solutions

Skills

Python

SystemVerilog

UVM

Lab instruments

Collaboration

Education

Bachelor's or Master's in Electrical Engineering

Tools

Cadence

Job description

Infineon Technologies AG in Austin, TX invites students and recent graduates to join WeAreIn in design and verification roles. You will assist with analog and digital design, develop testbenches, verify power management circuits, and perform silicon evaluation using Cadence tools. Strong Python, SystemVerilog, UVM, and Cadence experience are valued.

Collaboration across analog and digital teams is key. This entry-level role offers real projects, hands-on learning, and a pathway to future IP