Senior/Staff Analog Design Engineer - SerDes

OLIX; Austin (CO); On-site; USD 285,300 - 348,700; Full time

Benefits offered by this job

Competitive Salary

Stock options

Living-Local Bonus

Comprehensive healthcare

Employer-contributed retirement plans

Job summary

OLIX is actively seeking a Senior/Staff Analog Design Engineer in Austin, TX, to contribute to the development of high-speed SerDes and mixed-signal subsystems. This role spans the entire design lifecycle and requires strong hands-on circuit design skills.

With a focus on high-speed signaling fundamentals and collaboration with teams across locations, the ideal candidate will have over 10 years of experience in analog design. Competitive compensation of $317,000+ and comprehensive benefits are offered.

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Qualifications

• 10+ years of analog/mixed-signal IC design experience.
• Hands-on SerDes experience at data rates of 25 Gbps or higher.
• Solid understanding of jitter, noise, equalization, signal integrity, and link budgeting.

Responsibilities

• Architect and design high-speed SerDes blocks from specification through silicon.
• Perform schematic and post-layout simulations to ensure robust silicon margins.
• Collaborate with optical, digital, and system teams on interfaces and performance.

Skills

Analog mixed-signal design

SerDes experience

High-speed signaling concepts

Cadence Virtuoso

Verilog-A models

Communication skills

Education

MS or PhD in Electrical Engineering

Tools

Spectre

Job description

About OLIX

AI is growing faster than any technology in history and the explosion in demand has created a massive infrastructure gap; we can no longer build chips or power stations fast enough to keep up. The industry is still leaning on a ten-year-old hardware blueprint that has reached its limit. A new paradigm that is faster and more efficient will be the biggest economic opportunity of the next century and create the most important company of the next decade. The OLIX Decode Accelerator 1 (DX-1) is the first accelerator architected specifically for decode. Rack-scale co-design of logic, data movement, packaging, optics and interconnect enables a step change in system level performance.

The Role

We are seeking highly skilled and motivated Senior/Staff Analog Design Engineer to contribute to the development of high-speed SerDes and mixed-signal subsystems for a next-generation SoC. This role spans the full design lifecycle, from circuit implementation through post-silicon validation, across serializers, clock generation, equalization, and supporting analog blocks, requiring strong hands‑on circuit design skills and a solid grasp of high‑speed signaling fundamentals.

This is a highly collaborative, in‑office role based in Austin, TX, working closely with cross‑functional teams locally while also partnering with engineers in our London and Bristol offices to drive coordinated, global execution.

Responsibilities

• Architect and design high-speed SerDes blocks (serializers, TX drivers, TIAs, CTLEs, CDRs, deserializers, and clock generation) from specification through silicon in advanced FinFET nodes.
• Perform schematic and post‑layout simulations (including EM‑IR and reliability simulations) to ensure robust silicon margins, and own design reviews and documentation.
• Run EM simulations for passives, package interconnects, and on‑die routing.
• Develop behavioral and Verilog‑A models to enable system‑level and mixed‑signal verification.
• Supervise mask designers closely and provide floorplan and layout guidelines.
• Collaborate with optical, digital, and system teams on interfaces and link‑level performance.
• Support post‑silicon bring‑up, lab validation, and debug.

Skills & Experience

• MS or PhD in Electrical Engineering with 10+ years of analog/mixed‑signal IC design experience.
• Strong analog mixed‑signal design background with hands‑on SerDes experience at data rates of 25 Gbps or higher.
• Solid understanding of high‑speed signaling concepts: jitter, noise, equalization, signal integrity, and link budgeting.
• Expertise in advanced FinFET nodes with solid grasp of device physics, parasitics, and layout‑sensitive design.
• Proficiency with Cadence Virtuoso, Spectre, and industry‑standard simulation flows including PVT, Monte Carlo, EM‑IR, and reliability analysis.
• Experience developing behavioral and Verilog‑A models for mixed‑signal verification.
• Familiarity with post‑silicon bring‑up, lab measurement equipment, and correlating measured data to simulation.
• Strong communication skills and ability to collaborate across analog, digital, optical, and system teams.

Compensation & Equity

• Competitive Salary: $317,000+, commensurate with your experience, skills, and location.
• Equity & Ownership: Meaningful stock options. You’re not just joining the mission; you’re owning a piece of it.
• Proximity Bonus: We value your time. To minimise your commute and maximise your life, we offer an annual Living‑Local Bonus if your residence is within 20 minutes of the office.

Health, Wellbeing & Time Off

• Comprehensive healthcare, generous paid time off, and wellbeing support, with specific coverage and entitlements tailored to your location. For more information view here.

Retirement & Long-Term Savings

• Employer‑contributed retirement plans; 401(k) in the US, pension in the UK, and RRSP in Canada, to help you build long‑term financial security.

The Workspace & Tech

• M5 Macs come as standard, with M5 Pro upgrades for our engineering team. We will provide whatever you need to do your best work.
• High‑spec noise‑cancelling headphones and a fully ergonomic workstation designed for deep focus.
• Rapid Prototyping: Access to our high-performance 3D printing lab for work, experimentation, and personal creative projects.

Due to U.S. export control regulations, candidates’ eligibility to work at OLIX depends on their most recent citizenship or permanent residency status. We are generally unable to consider applicants whose most recent citizenship or permanent residence is in certain restricted countries (currently including Iran, North Korea, Syria, Cuba, Russia, Belarus, China, Hong Kong, Macau, and Venezuela). Applicants who have subsequently obtained citizenship or permanent residency in another country not subject to these restrictions may still be eligible.