Senior Analog Layout Designer — Equity & Impact

PassFort; Austin (TX); On-site; USD 120,000 - 180,000; Full time

Job summary

OLIX is seeking a Senior Analog Layout Designer to create RX/TX lane macros and support lane-level integration for the DX-1 accelerator. You will drive layout decisions across block and macro level, ensuring high-density, robust circuits for next-generation silicon.

Ideal candidates have 7+ years in analog layout, strong experience with FinFET processes, LVS/DRC/EM/IR verifications, and proficiency with Cadence Virtuoso and Calibre tools. Excellent communication and collaboration are essential.

Qualifications

• 7+ years of Analog Layout Design experience.
• “Understanding of the Semiconductor Fabrication process and device/layout cross-sections.”
• “Minimum 3 years of experience with the following TSMC FinFET processes: 2nm, 3nm, 4nm, 5nm.”
• “Several tape-outs with FinFET processes, owning major layout macros (ADC, DAC, TIA, CDR, PLL, BGB, LDO).”
• “Expert-level knowledge of block/macro floor-planning, block integration, routing, clock distribution, and power grid implementation.”
• “Expert-level knowledge of layout considerations for device matching, symmetry, parasitic reduction, and noise isolation.”
• “Expert-level knowledge of running and debugging LVS/ERC/DRC/Density/DFM/Antenna verifications.”
• “Expert-level knowledge of EM/IR analysis.”
• “Understanding of ESDs and Clamps, and their layout considerations.”
• “Understanding of layout effects such as LOD/OSE/PSE/WPE/MBE/LDE.”
• “Experience with lane integration and tape out versifications.”
• “Experience working with revision-controlled design libraries.”
• “Good communication skills.”
• “Knowledge of SKILL, TCL, and Python scripting is a plus.”

Responsibilities

• As a Senior Analog Layout Designer, you will be working to create layouts for RX/TX lane macros and support lane-level integration.

Skills

Analog layout design

Semiconductor fabrication

FinFET processes

Tape-out ownership

Floorplanning & routing

LVS/ERC/DRC

EM/IR analysis

Cadence Virtuoso

Calibre/Pegasus

ESD/clamps layout

Layout effects (LOD/OSE/PSE)

Lane integration

Revision-controlled libs

Communication skills

Scripting: SKILL/TCL/Python

Tools

Cadence Virtuoso

Calibre

Pegasus

LVS/DRC tools

Job description

OLIX is seeking a Senior Analog Layout Designer to create RX/TX lane macros and support lane-level integration for the DX-1 accelerator. You will drive layout decisions across block and macro level, ensuring high-density, robust circuits for next-generation silicon.

Ideal candidates have 7+ years in analog layout, strong experience with FinFET processes, LVS/DRC/EM/IR verifications, and proficiency with Cadence Virtuoso and Calibre tools. Excellent communication and collaboration are essential.