Senior Analog Layout Designer

PassFort; Austin (TX); On-site; USD 120,000 - 180,000; Full time

Job summary

OLIX is seeking a Senior Analog Layout Designer to create RX/TX lane macros and support lane-level integration for the DX-1 accelerator. You will drive layout decisions across block and macro level, ensuring high-density, robust circuits for next-generation silicon.

Ideal candidates have 7+ years in analog layout, strong experience with FinFET processes, LVS/DRC/EM/IR verifications, and proficiency with Cadence Virtuoso and Calibre tools. Excellent communication and collaboration are essential.

Qualifications

• 7+ years of Analog Layout Design experience.
• “Understanding of the Semiconductor Fabrication process and device/layout cross-sections.”
• “Minimum 3 years of experience with the following TSMC FinFET processes: 2nm, 3nm, 4nm, 5nm.”
• “Several tape-outs with FinFET processes, owning major layout macros (ADC, DAC, TIA, CDR, PLL, BGB, LDO).”
• “Expert-level knowledge of block/macro floor-planning, block integration, routing, clock distribution, and power grid implementation.”
• “Expert-level knowledge of layout considerations for device matching, symmetry, parasitic reduction, and noise isolation.”
• “Expert-level knowledge of running and debugging LVS/ERC/DRC/Density/DFM/Antenna verifications.”
• “Expert-level knowledge of EM/IR analysis.”
• “Understanding of ESDs and Clamps, and their layout considerations.”
• “Understanding of layout effects such as LOD/OSE/PSE/WPE/MBE/LDE.”
• “Experience with lane integration and tape out versifications.”
• “Experience working with revision-controlled design libraries.”
• “Good communication skills.”
• “Knowledge of SKILL, TCL, and Python scripting is a plus.”

Responsibilities

• As a Senior Analog Layout Designer, you will be working to create layouts for RX/TX lane macros and support lane-level integration.

Skills

Analog layout design

Semiconductor fabrication

FinFET processes

Tape-out ownership

Floorplanning & routing

LVS/ERC/DRC

EM/IR analysis

Cadence Virtuoso

Calibre/Pegasus

ESD/clamps layout

Layout effects (LOD/OSE/PSE)

Lane integration

Revision-controlled libs

Communication skills

Scripting: SKILL/TCL/Python

Tools

Cadence Virtuoso

Calibre

Pegasus

LVS/DRC tools

Job description

About OLIX

AI is growing faster than any technology in history and the explosion in demand has created a massive infrastructure gap; we can no longer build chips or power stations fast enough to keep up. The industry is still leaning on a ten-year-old hardware blueprint that has reached its limit. A new paradigm that is faster and more efficient will be the biggest economic opportunity of the next century and create the most important company of the next decade. The OLIX Decode Accelerator 1 (DX-1) is the first accelerator architected specifically for decode. Rack-scale co-design of logic, data movement, packaging, optics and interconnect enables a step change in system level performance.

Role

As a Senior Analog Layout Designer, you will be working to create layouts for RX/TX lane macros and support lane-level integration.

Skills and Experience

• 7+ years of Analog Layout Design experience

• Understanding of the Semiconductor Fabrication process and device/layout cross-sections

• Minimum 3 years of experience with the following TSMC FinFET processes: 2nm, 3nm, 4nm, 5nm

• Several tape-outs with FinFET processes, owning major layout macros (ADC, DAC, TIA, CDR, PLL, BGB, LDO)

• Expert-level knowledge of block/macro floor-planning, block integration, routing, clock distribution, and power grid implementation

• Expert-level knowledge of layout considerations for device matching, symmetry, parasitic reduction, and noise isolation

• Expert-level knowledge of running and debugging LVS/ERC/DRC/Density/DFM/Antenna verifications

• Expert-level knowledge of EM/IR analysis

• Expert-level knowledge of Cadence Virtuoso and Calibre/Pegasus verification tools

• Understanding of ESDs and Clamps, and their layout considerations

• Understanding of layout effects such as LOD/OSE/PSE/WPE/MBE/LDE

• Experience with lane integration and tape out versifications

• Experience working with revision-controlled design libraries

• Good communication skills

• Knowledge of SKILL, TCL, and Python scripting is a plus

Compensation & Equity

• Competitive Salary: Commensurate with your experience, skills, and location

• Equity & Ownership: Meaningful stock options. You're not just joining the mission; you're owning a piece of it

• Proximity Bonus: We value your time. To minimise your commute and maximise your life, we offer an annual Living-Local Bonus if your residence is within 20 minutes of the office

• Retirement Benefits: Employer-contributed retirement plans to help you build long-term financial security

Due to U.S. export control regulations, candidates’ eligibility to work at OLIX depends on their most recent citizenship or permanent residency status. We are generally unable to consider applicants whose most recent citizenship or permanent residence is in certain restricted countries (currently including Iran, North Korea, Syria, Cuba, Russia, Belarus, China, Hong Kong, Macau, and Venezuela). Applicants who have subsequently obtained citizenship or permanent residency in another country not subject to these restrictions may still be eligible.