Analog Design Engineer, Core Analog Blocks

Avicena Tech; Sunnyvale (CA); On-site; USD 140,000 - 200,000; Full time

Job summary

Avicena Tech is seeking an Analog Design Engineer to own core analog blocks across lanes, including references, bias, regulators, ESD and I/O. You will ensure low-noise, robust designs that withstand aging and corners, and drive blocks from spec to silicon.

Responsibilities cover design, verification, post-layout signoff, and support for silicon bring-up and characterization in a high-speed optical link context.

Qualifications

• MS in Electrical Engineering or BS with equivalent experience.
• 4+ years of analog design experience.
• Bandgap references, LDOs, bias circuits or ESD/I/O experience.
• Design experience in FinFET or other advanced CMOS processes.
• Proficiency with Cadence Virtuoso and Spectre and post-layout verification.

Responsibilities

• Design bandgap references, bias and current generators, and LDO regulators.
• Design ESD protection and general-purpose I/O circuits with layout and the package/SI-PI engineer.
• Design power-on reset, sequencing, temperature sensors and monitor circuits.
• Design analog test multiplexers and observability for production test and bring-up.
• Verify across PVT, Monte Carlo and aging, and check reliability including EM.
• Take blocks through post-layout extraction and signoff, and deliver behavioral models.
• Support silicon bring-up and characterization.

Skills

Analog design

IC design

LDO/bandgap

CMOS processes

Post-layout verification

Education

Master's in Electrical Engineering

Bachelor's in Electrical Engineering

Tools

Cadence Virtuoso

Spectre

Job description

Job Title

Analog Design Engineer, Core Analog Blocks

About The Role

Avicena is developing high-speed parallel optical links built from arrays of microLED transmitters and photodetector receivers. We are looking for an analog design engineer to own the core analog blocks every lane depends on: references, bias, regulators, ESD and I/O, monitors and test access. You will design robust, low-noise infrastructure and make sure it holds up across corners and over the product lifetime.

Key Responsibilities

• Design bandgap references, bias and current generators, and LDO regulators.
• Design ESD protection and general-purpose I/O circuits with layout and the package/SI-PI engineer.
• Design power-on reset, sequencing, temperature sensors and monitor circuits.
• Design analog test multiplexers and observability for production test and bring-up.
• Verify across PVT, Monte Carlo and aging, and check reliability including EM.
• Take blocks through post-layout extraction and signoff, and deliver behavioral models.
• Support silicon bring-up and characterization.

Qualifications

Required

• MS in Electrical Engineering (or BS with equivalent experience) and 4+ years of analog design.
• Taped-out bandgaps, LDOs, bias circuits or ESD/I/O.
• Design experience in FinFET or other advanced CMOS processes.
• Proficiency with Cadence Virtuoso and Spectre, and with post-layout verification.

Preferred

• ESD and latch-up design with foundry rules.
• On-die sensors and monitors.
• Low-noise supplies for high-speed circuits.
• Behavioral modeling in Verilog-A.

Key Competencies

• Robust design mindset: plans for corners, mismatch and aging.
• Ownership: carries blocks from specification to silicon.
• Collaboration: supports many block owners at once.
• Clear communicator: documents interfaces and limits.