Analog and Mixed Signal Design Engineer

Broadcom; Chandler (AZ); On-site; USD 110,000 - 176,000; Full time

Benefits offered by this job

Medical insurance

Dental plan

Vision plan

401(k) with company match

Employee Stock Purchase Program

Paid time off

Job summary

Broadcom’s Central Engineering Group is seeking a seasoned Mixed-Signal Analog Design Engineer to design on-die PVT monitoring IP and work across advanced process nodes.

You will handle circuit and layout activities, Verilog modeling, and IP documentation while driving post-silicon validation and test data analysis. This role requires strong collaboration and deep analog know-how.

Qualifications

• MS or PhD in Electrical Engineering required.
• 6+ years of mixed-signal and analog design experience required.
• Experience with Cadence Virtuoso and SPICE simulations is essential.

Responsibilities

• Circuit design & verification for analog/mixed-signal blocks.
• Layout supervision and post-layout validation using SPICE.
• Digital modeling and Verilog simulations for IPs.
• Documentation of datasheets and integration guides.
• Post-silicon testing guidance and data review.

Skills

Mixed-signal design

Analog design

Verilog modelling

Python scripting

Digital modeling

Education

MS or PhD in Electrical Engineering

Tools

Cadence Virtuoso

Spectre/HSPICE/PrimeSim

Synopsys PrimeTime

Verilog simulators (Xcelium/VCS)

Job description

Role Overview

Broadcom’s Central Engineering Group is seeking an experienced Mixed-Signal Analog Design Engineer to join our world-class team. In this position, you will design advanced on-die Process, Voltage, and Temperature (PVT) monitoring IP. You will work across a wide range of cutting-edge technologies, including the industry's most advanced process nodes and applications.

Job Description

Role Overview

Broadcom’s Central Engineering Group is seeking an experienced Mixed-Signal Analog Design Engineer to join our world-class team. In this position, you will design advanced on-die Process, Voltage, and Temperature (PVT) monitoring IP. You will work across a wide range of cutting-edge technologies, including the industry's most advanced process nodes and applications.

Responsibilities

• Circuit Design & Verification: Design schematic architectures for analog and mixed-signal blocks, including bandgaps, ADCs, DACs, voltage regulators, comparators, and GPIOs.
• Layout & Post-Layout Validation: Supervise layout design and verify post-layout design using SPICE simulations to ensure silicon success.
• Digital Modeling: Build behavioural and gate-level models for IPs and validate functionality through Verilog simulations.
• IP Delivery & Documentation: Create standard EDA tool views (including timing models), and author comprehensive datasheets and technical integration documents.
• Silicon Bring-up & Validation: Establish post-silicon testing guidelines and oversee the validation process by analysing and reviewing test data.

Education & Experience

• MS or PhD in Electrical Engineering
• 6+ years of mixed-signal and analog design experience.

Design Expertise

• Deep knowledge of core analog concepts including gain, bandwidth, stability, device physics, circuit reliability, process variation, and the statistical analysis of Monte Carlo simulation results.
• Strong understanding of layout effects on circuit performance.
• Familiarity with Verilog modelling, digital circuits, and standard digital implementation flows.

EDA Tools

• Proficiency with Cadence Virtuoso and simulation platforms like Spectre, HSPICE, or PrimeSim.
• Experience with Synopsys PrimeTime and Verilog simulators such as Xcelium or VCS.

Professional Attributes

• Excellent communication and teamwork skills.
• Proven ability to independently navigate complex, new, or unfamiliar engineering challenges.

Desired Skills

• Prior experience building and delivering mixed-signal IPs.
• General familiarity with laboratory testing methodologies and common bench equipment to effectively guide lab teams.
• Proficiency in scripting languages (Python, Perl, SKILL) to automate design and verification tasks.
• Familiarity with ESD (Electrostatic Discharge) and latch‑up design rules.
• Silicon Failure Analysis (FA) and debugging skills.

Compensation And Benefits

The annual base salary range for this position is USD 109,700.00 To USD 175,500.00

As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

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