AI SoC Power Architect — PPA & Thermal Leadership

EnCharge AI, Inc.; United States; Hybrid; USD 42,000 - 74,000; Full time

Job summary

EnCharge AI in Bengaluru seeks a Power Architect to drive end-to-end PPA excellence for next‑generation AI semiconductor chips. You will influence SoC architecture, RTL design, and physical layout to deliver industry‑leading power efficiency for AI inference and training workloads.

This cross‑functional role partners with design, architecture, and PD teams, shaping power intent, floorplanning, and tool flows to meet tight power budgets while pushing the envelope on efficiency.

Qualifications

• BS/MS/PhD in Electrical Engineering, Computer Engineering, or a related field.
• 12+ years of semiconductor experience focused on SoC architecture and low-power RTL design.
• Proven track record delivering complex, high-performance silicon under PPA constraints.
• Hands-on with power intent (UPF/CPF) and power estimation tools.
• Strong scripting for EDA tool automation (Python, Tcl, Perl).

Responsibilities

• Architectural Influence: Drive comprehensive SoC-level power and thermal management architecture.
• RTL & Floorplan Guidance: Review RTL implementation and collaborate with PD for area constraints and multi-voltage domains.
• PD Recipe Engineering: Develop and refine synthesis, placement, CTS, and routing recipes for best-in-class PPA.
• EDA & Custom Solutions: Drive adoption of power analysis tools and create custom scripts/workflows.
• Cross-Functional Collaboration: Lead PPA analysis across RTL, architecture, and PD teams to meet power budgets.

Skills

12+ years experience

SoC architecture

low-power RTL design

Physical Design

UPF/CPF

Power estimation

Python/Tcl/Perl

EDA tool flows

Education

BS/MS/PhD in Electrical/Computer Engineering

Tools

PowerArtist

PrimePower

Joules

Job description

EnCharge AI in Bengaluru seeks a Power Architect to drive end-to-end PPA excellence for next‑generation AI semiconductor chips. You will influence SoC architecture, RTL design, and physical layout to deliver industry‑leading power efficiency for AI inference and training workloads.

This cross‑functional role partners with design, architecture, and PD teams, shaping power intent, floorplanning, and tool flows to meet tight power budgets while pushing the envelope on efficiency.