AI-Powered Low-Power Silicon Validation Lead

NVIDIA; Santa Clara (CA); On-site; USD 168,000 - 311,000; Full time

Benefits offered by this job

Equity compensation

Benefits package

Career growth opportunities

Job summary

NVIDIA Silicon Co-Design Group is seeking a versatile engineer to redefine low-power silicon validation and system bring-up for AI and accelerated computing platforms. You will work at the intersection of silicon architecture, platform validation, firmware, telemetry, and productization to develop end-to-end methodologies and infrastructure for pre- and post-silicon readiness.

The role emphasizes scaling validation with AI-powered analytics, intelligent automation, telemetry pipelines, and

Qualifications

• BS/MS in EE, CE, CS, Systems Engineering, or equivalent experience.
• 10+ years of experience in silicon characterization, low-power feature validation, system integration, or post-silicon productization.
• Strong understanding of silicon power behavior, Windows/Linux low-power states, firmware interactions, power/performance tradeoffs, and system-level validation methodologies.
• Experience building scalable automation, telemetry analytics, or AI-assisted engineering workflows for silicon validation, debug, or productization.
• Strong EE fundamentals, including digital design, computer architecture, power analysis, statistics, and scripting/programming skills.
• Hands-on experience with silicon bring-up, lab validation, debug methodologies, and hardware lab instrumentation.
• Familiarity with AI/LLM-assisted engineering workflows, intelligent automation frameworks, telemetry analytics, or data-driven debug infrastructure.

Responsibilities

• Define the Power & Performance validation strategy across product lines, including power targets, rail budgets, and low-power feature validation methodologies.
• Build intelligent workload characterization frameworks that use telemetry, behavioral clustering, and AI-assisted analytics to improve validation coverage and expose power-state and data-path issues earlier in the development cycle.
• Define the instrumentation, counters, telemetry frameworks, and firmware hooks needed to support scalable silicon observability, automated validation, and AI-powered debug workflows prior to tapeout.
• Bring up and validate system-level low-power features across pre-silicon and post-silicon environments using sophisticated automation, data-driven validation methodologies, and generative AI-assisted debug techniques.
• Develop AI/ML-assisted infrastructure for telemetry analysis, anomaly detection, predictive validation analytics, workload optimization, automated triage, and cross-generation debug correlation.
• Partner closely with architecture, firmware, DV, HSIO, system integration, and data infrastructure teams to build scalable validation pipelines, intelligent dashboards, and modern engineering workflows for next-generation silicon platforms.
• Support manufacturing and customer-facing teams in resolving production and feature issues using telemetry-powered insights, automated analytics, and scalable debug methodologies.
• Work across hardware, software, firmware, and platform teams to drive low-power feature readiness from early architecture definition through silicon bring-up, validation, and product release.

Skills

Silicon characterization

Low-power validation

System bring-up

Automation scripting

Telemetry analytics

AI-assisted engineering

Python

Education

BS/MS in EE, CE, CS, Systems Engineering

Tools

Python

Job description

NVIDIA Silicon Co-Design Group is seeking a versatile engineer to redefine low-power silicon validation and system bring-up for AI and accelerated computing platforms. You will work at the intersection of silicon architecture, platform validation, firmware, telemetry, and productization to develop end-to-end methodologies and infrastructure for pre- and post-silicon readiness.

The role emphasizes scaling validation with AI-powered analytics, intelligent automation, telemetry pipelines, and