AI-Driven SSD Storage & Systems Architect

Engg; San Jose (CA); On-site; USD 180,000 - 260,000; Full time

Job summary

Samsung Semiconductor seeks an industry-leading SSD Storage and System Architect to design next‑generation Enterprise/DC/AI storage architectures. You will optimize AI data pipelines, model checkpointing, and high‑burst writes while aligning with hyperscale cloud clusters.

You’ll work with ASIC, firmware, and validation teams to push fast, low‑latency memory solutions and CXL/NVMe integrations, reporting to the Principal Engineer, R&D Product Development Planning.

Qualifications

• 10+ years in storage system architecture and related HDD/SSD domains.
• Experience aligning architecture with HPC or hyperscale datacenters.
• Proven contributions to storage/AI projects and open-source ecosystems.
• Strong communication and cross‑team leadership capabilities.

Responsibilities

• Define enterprise/DC/AI storage architectures optimized for AI workloads.
• Translate hardware/CXL constraints into firmware/IP for SSD controllers.
• Align features with hyperscaler AI infrastructure (Azure, AWS, Google).
• Collaborate with ASIC, firmware, and validation teams to remove bottlenecks.
• Prototype architectures with simulators/FPGA for evaluation.

Skills

Storage Architecture

PCIe/NVMe

CXL

GPUDirect Storage

ZNS/FDP

AI data pipelines

Cloud datacenter architecture

Technical leadership

Education

Bachelor’s degree in Electrical Engineering, Computer Engineering, CS

Master’s degree with 8+ years experience

PhD with 5+ years experience

Tools

NVMe controller knowledge

FPGA prototyping

Open-source storage projects

Job description

Samsung Semiconductor seeks an industry-leading SSD Storage and System Architect to design next‑generation Enterprise/DC/AI storage architectures. You will optimize AI data pipelines, model checkpointing, and high‑burst writes while aligning with hyperscale cloud clusters.

You’ll work with ASIC, firmware, and validation teams to push fast, low‑latency memory solutions and CXL/NVMe integrations, reporting to the Principal Engineer, R&D Product Development Planning.