AI Compiler Engineer for Custom Silicon & MLIR (Unlimited PTO)

River AI; Palo Alto (CA); On-site; USD 200,000 - 420,000; Full time

Benefits offered by this job

Health, dental, and vision benefits

Unlimited PTO

Relocation support

Job summary

River AI in Palo Alto or Austin is seeking an exceptional AI compiler engineer to bridge PyTorch graphs to our custom ISA. You will own kernel algorithms, IRs, and even ISA tweaks, collaborating with researchers and silicon architects.

You will design MLIR-based lowering passes, implement backends for our hardware, and optimize performance across the stack. The role requires a strong CS background and teamwork.

Qualifications

• Bachelor's degree in Electrical Engineering or Computer Engineering with 5+ years of relevant industry experience.
• Deep hands-on experience with MLIR or XLA for deep learning workloads.
• Expert-level understanding of PyTorch internals and integration with external backends.
• Proficiency in modern C/C++ for high-performance compiler infrastructure.
• Strong knowledge of computer architecture and various chip programming models.

Responsibilities

• Lower PyTorch models into custom hardware using MLIR dialects and LLVM-based tooling.
• Develop and maintain the backend toolchain for our silicon including scheduling and register allocation.
• Design tiling and fusion strategies to maximize bandwidth and minimize memory movement.
• Integrate high-performance kernels (Triton/CUDA-like) into the compiler flow.
• Collaborate with RTL, architecture, and performance teams to optimize ISA and compiler outcomes.

Skills

PyTorch internals

Collaborative mindset

Advanced computer architecture

Education

Bachelor’s degree in Electrical Engineering or Computer Engineering

Tools

MLIR

XLA

C/C++

LLVM-based toolchain

Job description

River AI in Palo Alto or Austin is seeking an exceptional AI compiler engineer to bridge PyTorch graphs to our custom ISA. You will own kernel algorithms, IRs, and even ISA tweaks, collaborating with researchers and silicon architects.

You will design MLIR-based lowering passes, implement backends for our hardware, and optimize performance across the stack. The role requires a strong CS background and teamwork.