AI Compiler Engineer, Custom Silicon

River AI Inc.; Austin, Palo Alto (TX, CA); On-site; USD 200,000 - 420,000; Full time

Benefits offered by this job

Visa sponsorship

Relocation assistance

Comprehensive benefits

Job summary

River AI Inc. is seeking exceptional AI compiler engineers to bridge PyTorch graphs to optimized custom ISA assembly. You will own kernel algorithms, IRs, and may modify the ISA to achieve a flexible, high-performance compiler stack.

Collaboration spans AI researchers, modelers, performance engineers, and silicon architects. You will design compiler passes, build backends for our silicon, and drive memory tiling/fusion strategies.

Qualifications

• Bachelor’s degree in Electrical or Computer Engineering with 5+ years industry experience.
• Hands-on MLIR or XLA experience for deep learning workloads.
• Proficiency in PyTorch internals and interfacing with backends.
• Strong C/C++ skills for compiler infrastructure.
• Deep knowledge of computer architecture and accelerator programming models.

Responsibilities

• Design and implement compiler passes to lower PyTorch models to custom hardware.
• Develop and maintain backend toolchain for custom silicon including instruction scheduling and register allocation.
• Design tiling and fusion strategies to maximize bandwidth and minimize on-chip movement.
• Integrate high-performance kernels (Triton/CUDA-like) into the compiler flow.
• Identify compilation gaps and work with performance team for targeted optimizations.
• Co-design with RTL and Architecture teams to evolve the custom ISA.

Skills

PyTorch internals

C/C++

MLIR / XLA

Computer architecture

Collaborative teamwork

Education

Bachelors in Electrical or Computer Engineering

Tools

LLVM

Job description

River AI Inc. is seeking exceptional AI compiler engineers to bridge PyTorch graphs to optimized custom ISA assembly. You will own kernel algorithms, IRs, and may modify the ISA to achieve a flexible, high-performance compiler stack.

Collaboration spans AI researchers, modelers, performance engineers, and silicon architects. You will design compiler passes, build backends for our silicon, and drive memory tiling/fusion strategies.