Kernel Engineer, Custom AI Silicon — Compute

River AI Inc.; Austin, Palo Alto (TX, CA); On-site; USD 200,000 - 420,000; Full time

Benefits offered by this job

Health, dental, and vision benefits

Unlimited PTO

Relocation support

Job summary

River AI Inc. is hiring a kernel engineer to build the foundational compute engine for its custom silicon. You will design and implement robust kernel generators and emit optimized assembly for our greenfield architecture.

You will collaborate with compiler engineers, silicon architects, and DL researchers to push compute efficiency, optimize GEMMs and attention ops, and ensure correctness on hardware simulations and silicon.

Qualifications

• Bachelor's degree in Computer Engineering, CS, or Electrical Engineering with 5+ years of industry experience in low-level performance programming.
• Deep understanding of hardware programming models (CUDA, Triton, CUTLASS) and a proven track record of shipping highly optimized kernels.
• Advanced knowledge of Computer Architecture, including vector units, execution pipelines, register files, and memory hierarchies (caches, SRAM, HBMs).
• Proficiency in modern C++ for building robust, scalable meta-programming and code-generation frameworks.
• Strong mathematical foundation in linear algebra and deep learning primitives.
• A highly collaborative mindset to push boundaries and co-design effectively with hardware and compiler teams.

Responsibilities

• Kernel Generator Development: Design and build C++ code-generation frameworks and meta-programming toolchains that automatically emit optimized custom ISA assembly code.
• Low-Level Compute Optimization: Author and optimize core deep learning primitives (GEMM/MatMul, Attention, Convolutions, and element-wise layers) for custom hardware.
• Microarchitectural Tuning: Hand-craft and automate instruction scheduling, register allocation, and software pipelining to maximize ALU utilization and hide latency.
• Memory Hierarchy Management: Design tiling, double-buffering, and data-movement strategies to maximize on-chip SRAM usage and minimize memory bottlenecks.
• HW/SW Co-Design: Partner with RTL/architecture teams to evaluate hardware simulations, provide ISA feedback, and influence future compute units.
• Performance Profiling & Validation: Benchmark generated assembly against hardware simulators and silicon; use performance counters to close gaps and ensure correctness.

Skills

Low-level performance programming

C++ metaprogramming

Hardware programming models

GEMM/MatMul

Tensor Core optimization

Collaboration with hardware/compiler

Education

Bachelor's degree in Computer Engineering/CS/EE

Tools

CUDA

Triton

CUTLASS

Custom ISA assembly

Job description

River AI Inc. is hiring a kernel engineer to build the foundational compute engine for its custom silicon. You will design and implement robust kernel generators and emit optimized assembly for our greenfield architecture.

You will collaborate with compiler engineers, silicon architects, and DL researchers to push compute efficiency, optimize GEMMs and attention ops, and ensure correctness on hardware simulations and silicon.