AI Accelerator Architect - Energy-Efficient LLM Compute

Normal Computing Corporation; Palo Alto (CA); On-site; USD 240,000 - 420,000; Full time

Job summary

Normal Computing seeks a Hardware Engineer, Architect to define silicon microarchitecture for a novel AI accelerator platform, driving energy efficiency leaps for LLM and diffusion model inference. You will translate workloads into hardware specs, collaborate across RTL, compiler, and analog teams, and lead pre-silicon validation strategies.

You will shape compute blocks, data paths, and interconnects, balancing performance, power, and area while keeping pace with cutting-edge AI research and

Qualifications

• A degree in Electrical Engineering, Computer Engineering, or Computer Science (PhD welcome).
• Experience shaping AI accelerator architectures and microarchitectures.
• Ability to translate workloads into datapath widths and power estimates.
• Experience with simulation-driven design and RTL collaboration.
• Familiarity with quantization and reduced-precision inference.

Responsibilities

• Define architecture and microarchitecture of AI accelerator compute blocks.
• Translate workload analysis into hardware specifications for RTL.
• Defend PPA tradeoffs across stack from algorithm to chip.
• Collaborate with compiler, RTL, and analog teams on design validation.
• Prototype pre-silicon validation with FPGA platforms.
• Stay current with AI accelerator research and differentiate Normal's approach.

Skills

AI accelerator design

Microarchitecture

Performance modeling

Python

C++

SystemVerilog

RTL collaboration

Quantization

Cycle-accurate modeling

Education

Electrical Engineering

Computer Engineering

Computer Science

Tools

RTL tooling

Job description

Normal Computing seeks a Hardware Engineer, Architect to define silicon microarchitecture for a novel AI accelerator platform, driving energy efficiency leaps for LLM and diffusion model inference. You will translate workloads into hardware specs, collaborate across RTL, compiler, and analog teams, and lead pre-silicon validation strategies.

You will shape compute blocks, data paths, and interconnects, balancing performance, power, and area while keeping pace with cutting-edge AI research and