AI Accelerator Hardware Architect

Normal Computing; Palo Alto (CA); On-site; USD 180,000 - 260,000; Full time

Job summary

Normal Computing is building foundational hardware and software for AI workloads. We seek a Hardware Engineer, Architect to define the silicon and system microarchitecture for an unconventional compute platform that aims for a 100–1000x energy efficiency leap over traditional chips, targeting LLM and diffusion model inference.

You will drive hardware/software co-design, translate transformer and diffusion execution flows into custom tiles, and work with RTL, compiler, and analog teams to

Qualifications

• Experience in architecture or microarchitecture of high‑performance digital systems such as AI accelerators
• Ability to translate workload analyses into hardware specifications and microarchitecture documents
• Experience with simulation-driven architecture and cycle-accurate models
• Understanding of quantization and reduced-precision implications for inference
• Experience writing microarchitecture specifications and collaborating with RTL teams

Responsibilities

• Define the silicon and system microarchitecture for the AI accelerator
• Translate workload analysis into hardware specifications and RTL-ready docs
• Balance PPA tradeoffs across algorithm, memory, interconnect and physical design
• Partner with compiler for ISA co-design and ensure alignment with research goals
• Direct pre-silicon prototyping and work with FPGA/design teams to de-risk tapeout
• Stay current with AI accelerator research and articulate differences of Normal’s approach

Skills

Microarchitecture

Performance modeling

RTL experience

Python/C++

SystemVerilog

Education

Bachelor's degree in Electrical/Computer Engineering or Computer Science

PhD welcome but not required

Tools

RTL tools

SystemVerilog

Job description

Normal Computing is building foundational hardware and software for AI workloads. We seek a Hardware Engineer, Architect to define the silicon and system microarchitecture for an unconventional compute platform that aims for a 100–1000x energy efficiency leap over traditional chips, targeting LLM and diffusion model inference.

You will drive hardware/software co-design, translate transformer and diffusion execution flows into custom tiles, and work with RTL, compiler, and analog teams to