Advanced Semiconductor/MEMS Layout & Routing Engineer - 1106

Quantinuum; Brooklyn Park (MN); On-site; USD 120,000 - 190,000; Full time

Job summary

Quantinuum in Brooklyn Park, MN, is seeking an Advanced Semiconductor/MEMS Layout & Routing Engineer to translate device concepts into manufacturable mask layouts from design to tapeout.

You will work with design engineers, fabrication scientists and external foundries to ensure layouts meet PDK requirements and design rules, leveraging Cadence Virtuoso, klayout and scripting. Candidates should have 5+ years IC/MEMS layout experience and be eligible to work in the U.S.

Qualifications

• Bachelor’s degree in a relevant engineering field.
• 5+ years IC/MEMS/PCB layout experience with advanced EDA tools.
• 2+ years with PDKs, layout hierarchy, routing, verification and tapeout.
• U.S. Person eligibility required.
• Knowledge of SKILL scripting and AI-assisted layout is a plus.

Responsibilities

• Develop and refine layout masks for ion trap devices.
• Collaborate with design engineers and foundries to meet PDK/design rules.
• Coordinate with external foundries for tapeout deliverables.
• Explore automation and AI/ML to speed up workflows.

Skills

IC/MEMS layout

PDK experience

Layout verification

Tapeout experience

SKILL scripting

AI/ML for layout

Education

Bachelor's degree

Tools

Cadence Virtuoso

klayout

L-Edit

PDK tooling

Job description

Advanced Semiconductor/MEMS Layout & Routing Engineer - 1106 at Quantinuum, US Brooklyn Park, MN. A executive-level full time position in the Quantum Computing Hardware team, listed under hardware engineering.

We are seeking an Advanced Semiconductor/MEMS Layout & Routing Engineer in our Brooklyn Park, MN, Albuquerque, NM or Broomfield, CO location.

Join an R&D team developing next-generation ion trap technologies. In this role, you will translate complex device concepts into manufacturable mask layouts, working from initial design through verification and tapeout. You will collaborate with design engineers, fabrication scientists, cross-functional partners, external foundries, and mask suppliers to ensure layouts meet technical requirements, established layout practices, and applicable process design kit requirements.

All applicants for placement in safety-sensitive positions will be required to submit to a pre-employment drug test.

WE VALUE

• Advanced degree in electrical engineering, computer science, computer engineering, mechanical engineering, physics or a related area preferred
• Experience laying out masks for multiple external (i.e., non-captive) foundries in multiple technologies, supporting PDK integration and design rule changes
• Familiarity with SKILL language script
• Photonics component layout, place and routing
• Familiarity with auto-routing tools in IC, PCB, MEMS layout and desire to leverage AI capabilities for layout
• Experience working in a cross-functional, R&D team environment.

Quantinuum is a leading quantum computing company delivering a full stack platform designed to make quantum computing deployable in real-world environments. With active engagements spanning pharmaceuticals, material science, financial services, government, industrial sectors, and leading academic and research institutions worldwide, we are helping organizations unlock the transformative potential of quantum computing.

Our global team of more than 800 employees includes many of the world's leading scientists, engineers, and researchers, with more than 70% of our technology team holding advanced degrees at the Master's or PhD level.

Responsibilities

• Develop and refine mask layouts for next-generation ion trap devices using Cadence Virtuoso, klayout, scripting and related layout tools.
• Partner closely with design engineers and fabrication scientists to resolve layout challenges and support device development through PDK and design rule refinement.
• Work directly with multiple external foundries to align layouts and tapeout deliverables with applicable PDKs, process requirements, and foundry best practices.
• Work with our layout team, vendors and foundries to refine workflows and help enable significant cycle time speedups through identifying areas for automation and AI/ML implementation

Requirements

• Bachelor’s degree minimum
• Minimum 5 years’ experience doing IC, MEMS or PCB layout using advanced EDA tools such as Cadence Virtuoso, Synopsis or L-Edit
• Minimum 2+ years’ experience with PDKs, layout hierarchy, routing, verification and tapeout processes
• Due to Contractual requirements, must be a U.S. Person. defined as, U.S. citizen permanent resident or green card holder, workers granted asylum or refugee status
• Due to national security requirements imposed by the U.S. Government, candidates for this position must not be a People’s Republic of China national or Russian national unless the candidate is also a U.S. citizen.