01. Physical Design Engineer

Neetha Consulting LLC; Cupertino (CA); On-site; USD 125,000 - 145,000; Full time

Job summary

Neetha Consulting LLC in USA is seeking a Physical Design Engineer to lead RTL to GDS implementation within an ASIC flow. You will own floorplanning, placement, CTS, routing, and timing closure for challenging nodes.

The role requires advanced IC design experience, collaboration with cross-functional teams, and scripting to automate flows. Expect travel to client sites as needed; strong proficiency with Innovus, Tempus, and PrimeTime is preferred.

Qualifications

• Master’s or foreign equivalent in Electrical Engineering, Computer Engineering, or related field.
• Ability to travel/relocate to client sites across the U.S.

Responsibilities

• Conceptualize, design, and productize advanced RTL to GDS implementations through ASIC design flow.
• Lead the physical design closure process including floorplanning, placement, clock tree synthesis, routing, and optimization.
• Develop IC block layouts optimized for area, timing, and power at advanced technology nodes (e.g., TSMC N5/N4P/N3).
• Drive implementation of high-performance, low-power, manufacturable designs.
• Perform synthesis, pre-layout STA, SDC constraints development, bump placement, power planning, MV design techniques, and UPF.
• Apply timing closure techniques: clock skew balancing, delay optimization, OCV handling, and ECO management.
• Conduct power and area optimization using Multi-Vt, clock gating, and power-aware synthesis.
• Manage post-layout STA, functional/timing ECOs, and high-frequency IP designs closure.
• Ensure physical verification (DRC, LVS, PERC, ERC, Antenna, EMIR, Power signoff) compliance with foundry sign-off standards.
• Collaborate with cross-functional teams to resolve design and manufacturing issues.
• Drive scripting and automation (Python, Perl, TCL) to enhance design efficiency.
• Use EDA tools (Innovus, ICCII, Fusion Compiler, Tempus, PrimeTime) for implementation and signoff readiness.

Skills

RTL to GDS

Floorplanning

Placement

Timing closure

Power optimization

Scripting

Cross-functional collaboration

Education

Master’s in Electrical Engineering or Computer Engineering

Tools

Innovus

ICCII

Fusion Compiler

Tempus

PrimeTime

Job description

• Full-time, 40 hours/week, Permanent position

Job Title:

Physical Design Engineer

Salary Range:

$125,000 – $145,000 per year (commensurate with experience)

Location:

USA

Job Duration:

40 hours/week, permanent position, full-time

Job Duties:

• Conceptualize, design, and productize advanced RTL to GDS implementations through ASIC design flow.
• Lead the physical design closure process including floorplanning, placement, clock tree synthesis, routing, and optimization.
• Develop efficient IC block layouts optimized for area, timing, and power at advanced technology nodes (e.g., TSMC N5/N4P/N3).
• Drive implementation of high-performance, low-power, manufacturable designs.
• Perform synthesis, pre-layout STA, SDC constraints development, bump placement, power planning, MV design techniques, and UPF.
• Apply timing closure techniques: clock skew balancing, delay optimization, OCV handling, and ECO management.
• Conduct power and area optimization using Multi-Vt, clock gating, and power-aware synthesis.
• Manage post-layout STA, functional/timing ECOs, and high-frequency IP designs closure.
• Ensure physical verification (DRC, LVS, PERC, ERC, Antenna, EMIR, Power signoff) compliance with foundry sign-off standards.
• Collaborate with cross-functional teams to resolve design and manufacturing issues.
• Drive scripting and automation (Python, Perl, TCL) to enhance design efficiency.
• Use EDA tools (Innovus, ICCII, Fusion Compiler, Tempus, PrimeTime) for implementation and signoff readiness.

Other Responsibilities:

• Mentor junior engineers and review design outputs.
• Document physical design flows, constraints, and reports.
• Implement and improve methodologies, workflows, and tools for better process quality and efficiency.

Job Requirements:

• Master’s or foreign equivalent in Electrical Engineering, Computer Engineering, or related field.
• Must be able to travel/relocate to various client sites across the U.S.

Location of Work:

Neetha Consulting LLC10080 North Wolfe Road, Suite SW3-200Cupertino, CA 95014