Testsite Engineer Intern: AI/EDA & Layout Automation

GlobalFoundries

Singapore

On-site

SGD 13,000 - 20,000

Full time

14 days+
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Job summary

GlobalFoundries invites interns to join its internship program, a pipeline for entry-level talent across the globe. Interns will receive one-on-one mentorship, growth opportunities, and the chance to network with executives during the program.

This internship role focuses on Hotwell design analysis, supporting test site layout development, and developing EDA automation solutions to improve design efficiency and reusability of test structures.

Qualifications

  • Actively pursuing a Bachelor’s or Master’s in Computer Science & Engineering or Electrical & Electronics Engineering during the internship.
  • Must be in good academic standing.
  • Ability to work at least 40 hours per week during the internship.
  • Available for a 16–24 week credit-bearing internship commencing January 2027.

Responsibilities

  • Understand Hotwell designs, test structures, and SLM macros.
  • Perform Hotwell design analysis to evaluate design characteristics and support testsite development activities.
  • Support layout design and development of test structures and testsite components.
  • Develop/update EDA code for automation and generation of test structures using ML/AI.
  • Consolidate and maintain existing code and test chip database.
  • Promote design reusability concepts to improve layout development efficiency.
  • Perform all activities safely and support Environmental, Health, Safety & Security requirements.

Skills

Interest in AI tools and emerging tech
Leadership experience

Education

Bachelor’s or Master’s in Computer Science & Engineering or Electrical & Electronics Engineering

Job description

GlobalFoundries invites interns to join its internship program, a pipeline for entry-level talent across the globe. Interns will receive one-on-one mentorship, growth opportunities, and the chance to network with executives during the program.

This internship role focuses on Hotwell design analysis, supporting test site layout development, and developing EDA automation solutions to improve design efficiency and reusability of test structures.

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