Lead Analog Layout Engineer – FinFET & SRAM

Trulyyy; Singapore; On-site; SGD 90,000 - 130,000; Full time

Job summary

Trulyyy in Singapore is seeking an Analog Layout Engineer to lead physical layout executions for high‑end ICs. You will drive floor planning, placement, and custom routing for analog and mixed‑signal macro modules, ensuring tight timing and power integrity.

The role requires hands‑on experience with sub‑8nm FinFET processes, DRC/LVS/ERC verification, and collaboration with design teams to deliver sign‑off ready layouts across mature and cutting‑edge nodes.

Qualifications

• 2–8 years of analog layout experience at OEMs, ODMs, or fabless companies.
• Hands-on experience with sub-8nm FinFET process nodes.
• Exposure to SRAM memory structures is a plus.

Responsibilities

• Lead floor planning, placement, and custom physical routing for analog and mixed-signal macro modules.
• Independently execute full physical verification suites (DRC, LVS, ERC).

Skills

Analog layout

Floor planning

Layout routing

Physical verification (DRC/LVS/ERC)

Education

Bachelor’s degree in electronic engineering or semiconductors

Tools

Design Rule Checking (DRC)

Layout Versus Schematic (LVS)

Electrical Rule Checking (ERC)

Job description

Trulyyy in Singapore is seeking an Analog Layout Engineer to lead physical layout executions for high‑end ICs. You will drive floor planning, placement, and custom routing for analog and mixed‑signal macro modules, ensuring tight timing and power integrity.

The role requires hands‑on experience with sub‑8nm FinFET processes, DRC/LVS/ERC verification, and collaboration with design teams to deliver sign‑off ready layouts across mature and cutting‑edge nodes.