SoC Physical Design Engineer – Full-Chip Tapeout Leader

ByteDance; Singapore; On-site; SGD 120,000 - 210,000; Full time

Job summary

ByteDance is seeking a Physical Design Engineer in Singapore to own the complete chip/SoC flow from planning to tapeout. You will shape die size, floorplanning, and hierarchical strategy, aligning blocks and subsystems for successful integration. Ideal candidates have 5+ years in PD, hands-on with ICC2 and Innovus, and experience on advanced nodes.

This role sits in the Technology team in Singapore with regular employment. Expect collaboration across global teams.

Qualifications

• BS degree in Electrical or Computer Engineering or equivalent practical experience.
• 5+ years of experience in physical design/physical implementation.
• Experience owning full chip/SoC physical implementation from planning to tapeout.

Responsibilities

• Own the full chip/SoC from early physical planning through final GDS/tapeout.
• Define the overall chip-level physical design strategy, including die size, utilization target, and floorplanning.
• Drive block partitioning, pin/bump planning, and clock architecture design.
• Establish hierarchical implementation methodology.
• Drive convergence across all physical-design blocks and subsystems.

Skills

Full-chip ownership

PD tool expertise

Clock architecture design

Hierarchical methodology

Education

BS in Electrical/Computer Engineering

Tools

Synopsys ICC2

Cadence Innovus

Job description

ByteDance is seeking a Physical Design Engineer in Singapore to own the complete chip/SoC flow from planning to tapeout. You will shape die size, floorplanning, and hierarchical strategy, aligning blocks and subsystems for successful integration. Ideal candidates have 5+ years in PD, hands-on with ICC2 and Innovus, and experience on advanced nodes.

This role sits in the Technology team in Singapore with regular employment. Expect collaboration across global teams.