SoC Front-End Design Engineer — RTL & Low Power

MaxLinear, Inc.; Singapore; On-site; SGD 90,000 - 130,000; Full time

Job summary

MaxLinear, Inc. is seeking a SoC Design Engineer to join the SoC Front-End Design team in Singapore. You will contribute to developing state-of-the-art ICs and IPs for wireless connectivity, focusing on RTL from specifications and high-quality implementation across multiple clock domains.

The role emphasizes low-power RTL, IP development for SoC and FPGA, and RTL2netlist collaboration with backend teams. Fresh graduates are welcome to apply, with opportunities to work on challenging DSP-related

Qualifications

• Bachelor or Master in Electrical/Electronics Engineering with IC design focus.
• Experience in the complete cycle of DSM (65, 45, 40, 28, 16nm) SoC Design, verification and tape-out with silicon validation.
• Experience in GPS, WLAN, BT, NFC, Ethernet, SoC/ARM/AHB bus design is a plus.
• Expert knowledge of low power inputs such as UPF/CPF and SoC connectivity tools has a strong advantage.

Responsibilities

• Design digital logic with VHDL/Verilog from specification.
• Develop high-quality RTL meeting input/output requirements, constraints, multi-clock domains, and modes.
• Design RTL with low power from standard power intent files.
• Produce RTL for SoC/FPGA-friendly and DFT-compliant code.
• Prepare RTL for IP development and SoC assembly.
• Support SoC Clock & Reset structures; engage in RTL2netlist collaboration.
• Verify designs with test-bench simulations and debug with FPGA prototyping.
• Leverage DFT and synthesis to improve design quality and performance.
• Collaborate with Backend teams to resolve design issues.

Skills

VHDL/Verilog

RTL design

Low power design

Synthesis

Test bench

FPGA prototyping

DFT experience

SoC/ARM/AHB bus

Education

Bachelor/Master in Electrical/Electronics Engineering

Tools

Core Consultant

Job description

MaxLinear, Inc. is seeking a SoC Design Engineer to join the SoC Front-End Design team in Singapore. You will contribute to developing state-of-the-art ICs and IPs for wireless connectivity, focusing on RTL from specifications and high-quality implementation across multiple clock domains.

The role emphasizes low-power RTL, IP development for SoC and FPGA, and RTL2netlist collaboration with backend teams. Fresh graduates are welcome to apply, with opportunities to work on challenging DSP-related