SoC Digital Design Engineer, Multimedia Lab

BYTEDANCE PTE. LTD.; Singapore; On-site; SGD 120,000 - 180,000; Full time

Benefits offered by this job

Paid leave

Meals provided

Competitive compensation

Career growth opportunity

Job summary

BYTEDANCE PTE. LTD. in Singapore is seeking a skilled video codec hardware design engineer to create RTL accelerators for FPGA/ASIC, focusing on high performance and scalable architectures. You will contribute to building industry‑leading video solutions for billions of users.

You will collaborate with algorithm, architecture, software, firmware and hardware design teams to drive verification, synthesis, timing, and power optimization across complex SoCs.

Qualifications

• Bachelor's degree or higher in Microelectronics, ICs, CS, Electrical Engineering, or related field.
• 3+ years of digital front‑end design experience (candidates with less may be considered if promising).
• Strong Verilog/SystemVerilog knowledge and solid digital circuit fundamentals.
• Proficiency with mainstream front‑end EDA tools (Spyglass, Design Compiler, PrimeTime).
• Fluent in at least one scripting language (Python, Perl, Tcl, Makefile) for automation.

Responsibilities

• Architecture Design: Define architecture of SoC top or subsystems and evaluate Power/Performance/Area early.
• RTL Implementation: Write high‑quality RTL (Verilog/SystemVerilog) and maintain design docs.
• Front‑End Quality Control: Run Lint, CDC, RDC checks to ensure code quality.
• Cross‑Functional Collaboration: Work with Verification, Backend/Mid‑end teams for synthesis, STA, power optimization.
• Low Power Design: Contribute to chip low‑power strategies and UPF flow.

Skills

Verilog/SystemVerilog

Scripting (Python, Perl, Tcl, Makefile

Education

Bachelor's degree or higher in Microelectronics/ICs/EE

Tools

Spyglass

Design Compiler

PrimeTime

Job description

Job Highlights

• Positive team atmosphere
• Career growth opportunity
• Paid leave
• 100+ mil users
• Meals provided
• Competitive compensation

Responsibilities

Our team is building industry‑leading, highly efficient, and scalable video codec hardware solutions (FPGA and ASIC) from the ground up to better serve billions of users. We are looking for strong video codec design engineers to design hardware accelerators for advanced video encoding and processing. The successful candidate will be part of a fast‑growing team that includes algorithm, architecture, software, firmware, and hardware design and verification experts with a dedication to technical excellence and a passion to build large‑scale and high‑performing video platforms and services.

1. Architecture Design: Participate in defining the architecture of SoC top or subsystems (NoC/CPU/NPU/ISP/Codec), and conduct PPA (Power, Performance, Area) evaluation during the early design phase.
2. RTL Implementation: Write high‑quality, well‑structured RTL code (Verilog/SystemVerilog) and maintain related design documentation.
3. Front‑End Quality Control: Perform Lint, CDC (Clock Domain Crossing), and RDC (Reset Domain Crossing) checks to ensure code standard compliance and design robustness.
4. Cross‑Functional Collaboration: Work closely with the Verification team for debugging and achieving Coverage closure; collaborate with the Backend/Mid‑end teams to support Synthesis, SDC (Synopsys Design Constraints) generation, STA (Static Timing Analysis), and power optimization.
5. Low Power Design: Participate in the formulation of chip low‑power strategies, proficiently apply Clock Gating and Power Gating techniques, and support the UPF (Unified Power Format) flow.

Minimum Qualifications

1. Bachelor's degree or higher in Microelectronics, Integrated Circuits, Computer Science, Electrical Engineering, or a related field.
2. 3+ years of experience in digital front‑end design (open to highly promising candidates with less experience).
3. Mastery of Verilog/SystemVerilog and a solid foundation in digital circuits.
4. Proficiency with mainstream front‑end EDA tools (e.g., Spyglass, Design Compiler, PrimeTime).
5. Fluent in at least one scripting language (Python, Perl, Tcl, Makefile) for workflow automation.

Preferred Qualifications

1. Deep understanding of NPU architecture, HW/SW co‑design and AI hardware acceleration.
2. Proven experience in SoC‑level performance profiling and bottleneck analysis.
3. Hands‑on experience in the integration of complex SoC core subsystems (e.g., CPU/NPU clusters, Memory subsystems).
4. Successful tape‑out experience in advanced process nodes (7nm/5nm/3nm)