Silicon Photonics Layout Engineer | Tape-Out Ready

Silith; Singapore; Hybrid; SGD 60,000 - 90,000; Full time

Job summary

Silith is seeking a Layout Engineer for its fabless silicon photonics design house in Singapore. You will transform circuit schematics into physical layouts ready for foundry tape-out, acting as the final checkpoint before silicon.

Expect close collaboration with design engineers to ensure layout meets performance and manufacturability goals. The role emphasizes photonic-aware layout and verification, with responsibilities spanning floor planning, rule-driven design, and tape-out support.

Qualifications

• Bachelor's degree in Microelectronics, Electronic Engineering, or related field.
• Minimum 1 year of experience in semiconductor industry.
• Proficient in reading and understanding foundry process flow and design rule documents.
• Experience with Python for layout design automation.
• Experience in writing Calibre DRC runset scripts.
• Tape-out process knowledge preferred.

Responsibilities

• Perform layout design from lower-level modules to top-level placement, routing, and verification.
• Communicate with design engineers to understand layout requirements, assist in floor planning, and complete layout for circuit modules and full-chip integration.
• Develop layout design guidelines and checklists for inspection, verification, and documentation archiving.
• Handle project tape-out activities.
• Other ad-hoc tasks as assigned by supervisors.

Skills

Foundry process knowledge

Python for automation

Layout verification

Calibre DRC scripting

Education

Bachelor's degree in Microelectronics or Electronic Engineering

Tools

Calibre

Job description

Silith is seeking a Layout Engineer for its fabless silicon photonics design house in Singapore. You will transform circuit schematics into physical layouts ready for foundry tape-out, acting as the final checkpoint before silicon.

Expect close collaboration with design engineers to ensure layout meets performance and manufacturability goals. The role emphasizes photonic-aware layout and verification, with responsibilities spanning floor planning, rule-driven design, and tape-out support.