Senior/Staff ASIC Design Engineer – Synthesis & Power

Bitdeer (NASDAQ: BTDR); Singapore; On-site; SGD 120,000 - 180,000; Full time

Job summary

Bitdeer, a world-leading technology company for Bitcoin mining and AI cloud, seeks an IC Design Engineer in Singapore. You will synthesize ASICs, optimize power and timing, and coordinate with physical design and verification teams to meet high-performance requirements.

The role requires 3–7 years of IC design experience, proficiency in Verilog/SystemVerilog, and strong scripting abilities. You will work in a dynamic, start-up styled environment that values initiative and collaboration.

Qualifications

• Bachelor’s or Master’s degree in Electrical or Computer Engineering or related field.
• 3–7 years of IC design experience focused on synthesis, timing closure, and power optimization.
• Proficient with Verilog/SystemVerilog and RTL-to-GDSII flow using major EDA tools.

Responsibilities

• Synthesize and optimize ASIC designs and perform timing closure.
• Conduct STA, constraint tuning, and clock tree synthesis for high-frequency paths.
• Collaborate with physical design and DFT teams on floorplanning, P&R, and JTAG integration.
• Verify correctness with formal methods and ensure low-power design techniques.

Skills

Verilog/SystemVerilog

TCL/Python scripting

Clock tree synthesis

Education

Bachelor’s or Master’s degree in Electrical Engineering or related field

Tools

Synopsys Design Compiler

Cadence Genus

PrimeTime

Innovus

Job description

Bitdeer, a world-leading technology company for Bitcoin mining and AI cloud, seeks an IC Design Engineer in Singapore. You will synthesize ASICs, optimize power and timing, and coordinate with physical design and verification teams to meet high-performance requirements.

The role requires 3–7 years of IC design experience, proficiency in Verilog/SystemVerilog, and strong scripting abilities. You will work in a dynamic, start-up styled environment that values initiative and collaboration.