Senior SoC Platform Quality Engineer: ATE Debug Lead

AUREXIS TECH PTE. LTD.; Singapore; On-site; SGD 90,000 - 140,000; Full time

Job summary

AUREXIS TECH PTE. LTD. in Singapore seeks an engineer to lead or contribute to component debug for customer-return and manufacturing-test failures using production ATE and electrical characterization methods.

You will analyze ATE datalogs and failure signatures, develop experiments and optimization plans, and drive root-cause investigations with cross-functional teams. Proficiency in Python/C++/Tcl/Perl or Verilog/VHDL is required with strong Linux knowledge.

Qualifications

• Degree in Electrical, Electronics or Computer Engineering or equivalent with 3+ years of relevant experience.
• Experience in ATE debug for x86, CPU, SoC or other complex digital semiconductor products.
• Strong understanding of VERIGY 93K based test-program architecture, development and execution.
• Experience debugging test programs, test methods, patterns, vectors, functional failures and limit-related issues.
• Experience interpreting tester datalogs, design and run DOE for failure-signature analysis.
• Working knowledge of DFT concepts including ATPG scan, scan compression, logic diagnosis, memory BIST and JTAG/boundary scan.
• Debug of high-speed interfaces such as PCIe, DDR, USB, SATA or Ethernet using ATE-based methods.
• Strong knowledge of digital logic, circuit analysis, CMOS fundamentals, semiconductor device behavior and electrical failure mechanisms is highly desirable.
• Proficiency in at least one relevant language: Python, C/C++, Tcl, Perl, Verilog, VHDL or Unix shell.
• Working knowledge of Linux and structured engineering data analysis.
• Experience integrating AI agents into daily workflows is highly desirable.

Responsibilities

• Lead or contribute to component debug for customer-return and manufacturing-test failures using production ATE and electrical characterization methods.
• Debug and optimize ATE test programs, test methods, test limits, levels, timings and production test flows.
• Analyze ATE datalogs, failure signatures, shmoo results and characterization data to isolate silicon, design, test, process or application-related causes.
• Develop and execute electrical experiments and characterization plans to validate hypotheses.
• Drive root-cause investigations, containment, corrective actions and recurrence prevention.
• Develop automation, data-analysis and diagnostic tools using Python, C/C++, Tcl, Perl or Unix shell scripting.
• Prepare clear technical reports and communicate conclusions, risk and recommended actions to engineering and management stakeholders.
• Lead cross-functional technical projects appropriate to the assigned job level and mentor engineers in ATE debug and failure-analysis methods.

Skills

ATE debugging

Python

C/C++

Tcl

Perl

Verilog

VHDL

Linux

JTAG/Boundary scan

DOE

PCIe

Education

Electrical, Electronics or Computer Engineering degree or equivalent

Tools

VERIGY 93K

Linux

Job description

AUREXIS TECH PTE. LTD. in Singapore seeks an engineer to lead or contribute to component debug for customer-return and manufacturing-test failures using production ATE and electrical characterization methods.

You will analyze ATE datalogs and failure signatures, develop experiments and optimization plans, and drive root-cause investigations with cross-functional teams. Proficiency in Python/C++/Tcl/Perl or Verilog/VHDL is required with strong Linux knowledge.