Senior SoC Design Verification Lead

Bitdeer; Singapore; Sur place; SGD 120 000 - 180 000; Plein temps

Résumé du poste

Bitdeer is seeking a Design Verification Lead to steer the verification strategy for complex IC designs in Singapore. You will lead a team of verification engineers to ensure robust coverage, high-quality silicon, and scalable automation through modern verification methodologies.

You will collaborate with design and architecture teams, develop verification environments and test plans, drive regression, and mentor junior engineers to raise the team's capability and delivery reliability.

Qualifications

• At least 10 years of relevant experience in IC/SoC functional verification.
• Strong debugging skills with RTL simulation and waveform analysis tools.
• Proficient in UVM, SystemVerilog, Verilog, and SVA languages; strong knowledge in AXI, NoC, RISC-V.
• Proven ability to lead verification efforts and mentor engineers.
• Excellent communication and collaboration skills in cross-functional development environments.

Responsabilités

• Lead the verification strategy and execution for assigned DUT blocks, ensuring comprehensive functional coverage and high verification quality.
• Guide and mentor the verification team in developing, reviewing, and maintaining detailed verification test plans aligned with design specifications and architecture requirements.
• Develop and implement verification environments, testbenches, and test sequences based on modern verification methodologies.
• Drive the creation of test patterns and stimulus scenarios to thoroughly validate DUT functionality and corner cases.
• Run simulations, analyze results, and debug RTL issues in close collaboration with design engineers.
• Manage and execute regression testing to ensure design stability across feature updates and bug fixes.
• Track, analyze, and improve functional and code coverage metrics, enabling coverage-driven verification and sign-off readiness.
• Ensure clear and comprehensive verification documentation, including test cases, results, coverage reports, and verification sign-off.
• Develop and enhance automation scripts, reusable verification components, and Verification IP (VIP) to improve team productivity and scalability.
• Work cross-functionally with design, architecture, and physical implementation teams to resolve issues and achieve timely project milestones.
• Mentor and provide guidance to help in developing more junior team member

Connaissances

UVM

SystemVerilog

Verilog

SVA

AXI

NoC

RISC-V

RTL simulation

waveform analysis

leadership

Formation

Bachelor's degree in Microelectronics or related fields

Outils

VIP

Testbenches

Description du poste

Bitdeer is seeking a Design Verification Lead to steer the verification strategy for complex IC designs in Singapore. You will lead a team of verification engineers to ensure robust coverage, high-quality silicon, and scalable automation through modern verification methodologies.

You will collaborate with design and architecture teams, develop verification environments and test plans, drive regression, and mentor junior engineers to raise the team's capability and delivery reliability.