Senior Process Integration Engineer - Yield & Quality

STATS CHIPPAC MANAGEMENT PTE. LTD.; Singapore; On-site; SGD 70,000 - 110,000; Full time

Job summary

STATS CHIPPAC MANAGEMENT PTE. LTD. is seeking a Process Integration professional to oversee process engineers and drive yield enhancement and quality improvements in wafer bumping, fabrication, or packaging. You will collaborate with AOI/equipment teams and leverage DOE/SPC methodologies.

The role requires a physics/engineering background with 5–10 years of wafer process experience and a proven track record in process optimization and problem solving. This on-site position is based in Singapore.

Qualifications

• Degree in Physics, Chemistry, Materials Science, Mechanical/Chemical/Electrical Engineering or equivalent.
• 5 to 10 years of relevant experience in wafer bumping, wafer fabrication or packaging.
• Strong knowledge in process integration scheme, process stability and yield enhancement.

Responsibilities

• Contain high Defect Density and inline excursions; identify root causes and implement solutions to satisfy customer quality.
• Review unresolved requests for adjustment of complaints and plan actions to resolve.
• Drive process improvement based on analysis of inline/electrical test/yield data to meet quality and yield targets.
• Identify key process weaknesses and fine-tune processes for yield/quality/productivity and cost.
• Use DOE, SPC and 8D, 5 Whys to determine root causes for low yields and develop containment/preventive actions.
• Lead process control plan updates and customer audits.
• Support new process/product qualification from design to LVM completion.

Skills

DOE

SPC

Root cause analysis

Problem solving

Process optimization

Data analysis

Quality improvement

Education

Physics

Chemistry

Materials Science

Mechanical Engineering

Chemical Engineering

Electrical Engineering

Job description

STATS CHIPPAC MANAGEMENT PTE. LTD. is seeking a Process Integration professional to oversee process engineers and drive yield enhancement and quality improvements in wafer bumping, fabrication, or packaging. You will collaborate with AOI/equipment teams and leverage DOE/SPC methodologies.

The role requires a physics/engineering background with 5–10 years of wafer process experience and a proven track record in process optimization and problem solving. This on-site position is based in Singapore.