Senior Physical Verification CAD Engineer (2.5D/3D IC)

PERSOL Singapore; Singapore; On-site; SGD 85,000 - 125,000; Full time

Job summary

PERSOL Singapore is seeking an engineer to join the IC design verification team. You will work with the PDK group to code and maintain DRC, LVS, ANT, ERC, LPE, and ESD rule decks for multiple processes, and you will help develop layout and physical verification flows.

You will collaborate with QA to reduce defects in PDKs and rule decks, perform full-chip physical verification, and implement automation scripts using C-shell, Python, and Perl.

Qualifications

• Bachelor/Master's degree in Electrical/Electronics Engineering or Computer Science.
• Familiarity with IC design front-to-backend flow.
• Hands-on experience with interposer design, TSV technology and 2.5D/3D IC stacking (CoWoS/EMIB) is a must.
• Proficiency in scripting languages (Tcl, Python, Perl) and UNIX/Linux environments.

Responsibilities

• Code and maintain DRC/LVS/ANT/ERC/LPE/ESD rule decks for multiple processes.
• Develop layout implementation and physical verification flows.
• Collaborate with QA to reduce PDK and rule deck defects.
• Perform full-chip physical verification and debugging of DRC/LVS/ERC.
• Implement automation scripts in shell, Python and Perl.

Skills

Electrical Engineering

IC Design

Scripting

UNIX/Linux

Communication

Problem Solving

Education

Bachelor/Master's Degree in Electrical/Electronics/CS

Tools

Calibre

ICV

Job description

PERSOL Singapore is seeking an engineer to join the IC design verification team. You will work with the PDK group to code and maintain DRC, LVS, ANT, ERC, LPE, and ESD rule decks for multiple processes, and you will help develop layout and physical verification flows.

You will collaborate with QA to reduce defects in PDKs and rule decks, perform full-chip physical verification, and implement automation scripts using C-shell, Python, and Perl.