Senior PCIe PHY Lead: Gen5/6 Validation & Debug

MaxLinear, Inc.; Singapore; On-site; SGD 180,000 - 240,000; Full time

Job summary

MaxLinear, Inc. seeks a Senior Principal PCIe PHY Validation Engineer to lead high-speed PCIe validation, characterize PHY behavior, and drive compliance readiness for PCIe Gen5/Gen6 in advanced storage and networking platforms.

You will own validation plans, coordinate with silicon, firmware, and systems teams, and guide debugging and manufacturing support to ensure production readiness and robust interop across real platforms.

Qualifications

• Experience validating PCIe PHYs or high-speed SerDes at silicon, board, or system level.
• Lab proficiency with high-bandwidth oscilloscopes, BERTs, protocol analyzers, and pattern generators.
• Knowledge of PCIe electrical concepts (eye margin, jitter, CTLE/DFE, SSC, channel loss).
• Ability to debug complex interactions across PHY, firmware, BIOS, host platforms, and boards.
• Strong data analysis and automation skills with Python and lab APIs.

Responsibilities

• Define PCIe PHY validation strategy and pass/fail criteria.
• Lead hands-on electrical characterization and observe eye/jitter behavior.
• Lead modeling and simulation of PCIe Gen5/Gen6 interfaces.
• Drive PCIe bring-up, debug, and failure isolation.
• Prepare PCIe compliance and interoperability testing ahead of events.
• Support manufacturing and customers during ramps and data-driven issues.
• Be the technical authority for PCIe PHY validation and mentor engineers.

Skills

PCIe validation

SerDes interfaces

Lab instrumentation

Jitter/eye diagrams

Python automation

Cross-functional leadership

Tools

Oscilloscopes

BERTs

Pattern generators

Protocol analyzers

Cadence Allegro

Job description

MaxLinear, Inc. seeks a Senior Principal PCIe PHY Validation Engineer to lead high-speed PCIe validation, characterize PHY behavior, and drive compliance readiness for PCIe Gen5/Gen6 in advanced storage and networking platforms.

You will own validation plans, coordinate with silicon, firmware, and systems teams, and guide debugging and manufacturing support to ensure production readiness and robust interop across real platforms.