Senior Principal PCIe PHY & PI Architect (Gen5/6)

MaxLinear; Singapore; On-site; SGD 180,000 - 240,000; Full time

Job summary

MaxLinear seeks a Senior Principal PCIe PHY Validation Engineer to lead hands-on electrical validation, compliance readiness, and system-level debug for high-speed PCIe interfaces used in cutting-edge hardware platforms optimized for high-performance storage accelerator solutions.

You will own validation strategy for PCIe Gen5/Gen6, mentor engineers, and collaborate with silicon design, firmware, systems, board design, SI/PI, manufacturing, and customers to ensure robust implementations.

Qualifications

• Experience validating PCIe PHYs or high-speed SerDes at silicon, board, or system level.
• Strong lab instrumentation and test-plan development skills.
• Ability to translate PCIe specs into executable lab tests and pass/fail criteria.
• Experience with LTSSM analysis and board-level debugging.

Responsibilities

• Define validation plans for PCIe PHY electrical characterization and compliance readiness.
• Lead hands-on electrical characterization and analyze eye diagrams and jitter.
• Mentor engineers and communicate risk and recommendations to leadership.
• Plan and execute production-ready PCIe validation for HHHL and form-factor boards.

Skills

PCIe PHY validation

Eye-diagram analysis

Python automation

Cross-functional leadership

High-speed SerDes

Tools

Cadence Allegro

Oscilloscopes

Protocol analyzers

BERTs

Job description

MaxLinear seeks a Senior Principal PCIe PHY Validation Engineer to lead hands-on electrical validation, compliance readiness, and system-level debug for high-speed PCIe interfaces used in cutting-edge hardware platforms optimized for high-performance storage accelerator solutions.

You will own validation strategy for PCIe Gen5/Gen6, mentor engineers, and collaborate with silicon design, firmware, systems, board design, SI/PI, manufacturing, and customers to ensure robust implementations.