Senior Engineer - Design Enablement & Ground Rules (GRV)

GlobalFoundries; Singapore; On-site; SGD 60,000 - 90,000; Full time

Job summary

GlobalFoundries is seeking an RF Design Enablement engineer focused on Ground Rule Validation (GRV). You will contribute to ground rule development and silicon validation as part of the Design Manual Engineering team, collaborating with US, German, and Singapore sites.

You will build DoE layouts, perform rigorous silicon data analysis, and communicate findings to Design Rule engineers and integration teams, helping to optimize GF’s technology portfolio.

Qualifications

• BSEE or higher in electrical engineering or related field.
• Strong data analysis, data mining and problem-solving skills.
• Understanding of semiconductor fabrication flow and DOE methods.
• Strong interpersonal and communication skills; team player.
• Familiarity with Cadence Virtuoso and Calibre is a plus.

Responsibilities

• Collaborate with program managers and manufacturing teams to define key design-rule features.
• Create layout DoE and test structures for delivery on test vehicles.
• Perform silicon data analysis and share conclusions with design-rule and integration teams.
• Champion process or design-rule modifications to optimize GF technology portfolio.
• Follow safety, health, and environmental requirements and related programs.
• After GRV training, work on technologies manufactured in Fab9/8 (US) or Singapore.
• Validate transfer technologies to ensure compatibility of Design Rules with fabrication lines.

Skills

Data analysis

DOE methodology

Problem solving

Interpersonal skills

Communication

Education

BSEE in Electrical Engineering

MS in Electrical Engineering

PhD in Electrical Engineering

Tools

Cadence Virtuoso

Calibre (DRC/LVS)

Virtuoso Layout Suite

Job description

GlobalFoundries is seeking an RF Design Enablement engineer focused on Ground Rule Validation (GRV). You will contribute to ground rule development and silicon validation as part of the Design Manual Engineering team, collaborating with US, German, and Singapore sites.

You will build DoE layouts, perform rigorous silicon data analysis, and communicate findings to Design Rule engineers and integration teams, helping to optimize GF’s technology portfolio.