Senior DDR PHY Design Engineer — High-Speed Analog & SI

Brightecs Innovation Pte Ltd; Singapore; On-site; SGD 120,000 - 160,000; Full time

Job summary

Brightecs Innovation Pte. Ltd. is seeking an experienced engineer to design high-speed analog circuits for DDR PHY interfaces (DDR4/DDR5/LPDDR5/6) in Singapore.

You will optimize PPA and SI while delivering robust silicon through JEDEC-compliant methods and advanced node implementations. Responsibilities include modeling channel losses, crosstalk, jitter and eye diagrams, designing impedance-matching networks, and collaborating with layout, digital, verification and firmware teams to ensure

Qualifications

• Bachelor’s degree or above in Electrical and Electronic Engineering (EEE).
• 8+ years of relevant experience in similar field in semiconductor industry.

Responsibilities

• Design high-speed analog circuits for DDR PHY interfaces (DDR4/DDR5/LPDDR5/6).
• Optimize power, performance, area (PPA) and signal integrity (SI).
• Model and simulate channel losses, crosstalk, jitter, and eye diagrams.
• Ensure JEDEC DDR5-6400 MT/s compliance.
• Design impedance-matching networks and noise-suppression circuits.
• Implement designs in FinFET/7nm/5nm nodes; address PVT variations and reliability (TDDB, EM/IR).
• Collaborate with layout on floor planning, matching and parasitic extraction.
• Develop test plans for lab characterization and ATE; debug silicon with oscilloscopes, BERTs, protocol analyzers.
• Perform shmoo plotting, margin analysis, and yield improvement.
• Collaborate with digital design, verification, and firmware teams for PHY integration; support package/PCB teams; document specs and test results.

Skills

DDR protocols

Analog design

Signal integrity

High-speed I/O

PPA optimization

Cross-functional collaboration

Education

Bachelor’s degree in Electrical and Electronic Engineering

Tools

Cadence Virtuoso

Cadence Spectre

HSPICE

ADS

EMX

Job description

Brightecs Innovation Pte. Ltd. is seeking an experienced engineer to design high-speed analog circuits for DDR PHY interfaces (DDR4/DDR5/LPDDR5/6) in Singapore.

You will optimize PPA and SI while delivering robust silicon through JEDEC-compliant methods and advanced node implementations. Responsibilities include modeling channel losses, crosstalk, jitter and eye diagrams, designing impedance-matching networks, and collaborating with layout, digital, verification and firmware teams to ensure