Senior Analog Design Engineer

Trulyyy; Singapore; On-site; SGD 60,000 - 120,000; Full time

Job summary

Trulyyy in Singapore is seeking an Analog Designer to define specifications and execute transistor-level design for critical analog building blocks.

You will perform pre- and post-layout verification and work closely with layout engineers on device matching, shielding, and floorplanning sign-off. A strong background in LDO/BGR/POR or precision clock generation with Cadence Virtuoso is essential.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering or equivalent with hands-on analog IP experience.
• Experience driving custom analog IPs from specification to tape-out.
• Strong background in power management (LDO, BGR, POR) or precision clock generation using Cadence Virtuoso.

Responsibilities

• Define specifications and perform transistor-level design for analog building blocks.
• Conduct pre- and post-layout verification.
• Collaborate with layout engineers on device matching, shielding, and floorplanning sign-off.

Skills

Analog IP design

Transistor-level design

Pre-layout verification

Floorplanning

Device matching

Sign-off procedures

Education

Bachelor's or Master's in Electrical Engineering

Tools

Cadence Virtuoso

SPICE

Job description

About the Role

Join a global leader in chip manufacturing. We are looking at Analog designers that mainly works on serdes blocks and ASIC products.

Key Responsibilities

• Define specifications and execute precision transistor-level design for critical analog building blocks
• Perform comprehensive pre- and post-layout verification
• Collaborate directly with physical layout engineers on critical device matching, shielding, and floorplanning sign-off

Requirements

• Bachelor's or Master's degree in Electrical Engineering (or equivalent) with hands-on experience driving custom analog IPs from architectural specification through successful tape-outs.
• Deep functional background designing power management circuits (LDO, BGR, POR) or precision clock generation components using standard Cadence Virtuoso and SPICE simulation flows
• Experience supervising floorplanning, matching, and parasitic mitigation, alongside a strong command of physical sign-off procedures (DRC, LVS, ERC).

Regrettably, only shortlisted candidates will be notified.

Please note that data provided is for recruitment purposes only.

Business Registration No.: 202004228R | License No.: 20S0118 | EA Registration No.: R2210710