Senior 3DIC Packaging Engineer - Tapeout & 3D Integration

Bitdeer Technologies Group

Singapore

On-site

SGD 120,000 - 180,000

Full time

14 days+

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Job summary

Bitdeer is hiring a senior 3DIC engineer in Singapore to own TSV/hybrid bonding definitions and drive 3D floorplan decisions across foundry and memory partners. The role requires deep experience with TSV, 3D stacking, and DFM/3D design rules, ensuring reliability through tapeout.

You will coordinate thermal analyses, SI/PI at die-to-die interfaces, and signoff readiness, working closely with DFT and OSAT teams to deliver a robust 3D integration strategy.

Qualifications

  • 5+ years in 3DIC / advanced-packaging with at least one product taped out.
  • Hands-on TSV and hybrid bonding experience; 3D stacking flow.
  • Experience with 3DFabric SoIC/CoWoS and related design kits.
  • Solid knowledge of thermal/thermo-mechanical and SI/PI at die-to-die interface.
  • Ability to own cross-organization interfaces with foundry and OSAT.

Responsibilities

  • Own the TSV/hybrid-bond interface definitions with foundry partners.
  • Drive 3D-aware floorplan inputs and die-to-die placement.
  • Define and close DFM and 3D design rules; review constraints.
  • Coordinate thermal and mechanical analysis and feed mitigations into floorplan.
  • Drive 3D signoff for thermal and SI/PI; ensure tapeout readiness.
  • Collaborate on 3D test strategies with the DFT team.
  • Manage package/substrate co-design handoff to OSAT.
  • Track deliverables and milestones with memory partner; surface risks early.

Skills

3DIC
TSV
Hybrid bonding
DFT
Thermal analysis
SoIC/CoWoS

Education

PhD/MS in EE

Tools

Ansys
Synopsys
Cadence

Job description

Bitdeer is hiring a senior 3DIC engineer in Singapore to own TSV/hybrid bonding definitions and drive 3D floorplan decisions across foundry and memory partners. The role requires deep experience with TSV, 3D stacking, and DFM/3D design rules, ensuring reliability through tapeout.

You will coordinate thermal analyses, SI/PI at die-to-die interfaces, and signoff readiness, working closely with DFT and OSAT teams to deliver a robust 3D integration strategy.

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