Principal Engineer – CMOS Device & Process Optimization

MICRON SEMICONDUCTOR ASIA OPERATIONS PTE. LTD.; Singapore; On-site; SGD 90,000 - 150,000; Full time

Job summary

Micron Semiconductor Asia Operations Pte. Ltd. is seeking a seasoned engineer to drive technology ramps in high-volume CMOS and memory production.

The ideal candidate will apply data analysis to reduce variability, collaborate across functions to optimize designs and tests, and lead process improvements to boost manufacturability and performance. Applicants should have 5+ years in wafer fab or process integration, with preference for FinFET/GAA CMOS experience, strong semiconductor physics

Qualifications

• Minimum 5 years of relevant experience.
• Master's or PhD in Physics or Engineering preferred.
• Experience in wafer fab process or process integration engineering.
• Direct experience in advanced CMOS device technology such as FinFET or GAA preferred.
• Knowledge of semiconductor physics and transistor operation.
• Understanding of wafer fabrication process areas, tool sets and tuning knobs.
• Programming capability such as Python is a plus.
• Occasional international travel is required.

Responsibilities

• Enable technology ramp in high-volume production for CMOS and memory devices.
• Improve device performance with a focus on variability reduction and robustness.
• Support and execute design and test optimisation to enhance manufacturability and performance.
• Identify and implement process simplification and working methodology improvements.
• Lead or actively contribute to cross-functional problem-solving for device, yield, and quality issues.

Skills

Data analysis

Python

MS Office

Problem solving

Teamwork

Education

Master's or PhD in Physics or Engineering

Tools

JMP

Spotfire

Job description

Micron Semiconductor Asia Operations Pte. Ltd. is seeking a seasoned engineer to drive technology ramps in high-volume CMOS and memory production.

The ideal candidate will apply data analysis to reduce variability, collaborate across functions to optimize designs and tests, and lead process improvements to boost manufacturability and performance. Applicants should have 5+ years in wafer fab or process integration, with preference for FinFET/GAA CMOS experience, strong semiconductor physics