Physical Design Engineer

SVENTL ASIA PACIFIC PTE. LTD.; Singapore; On-site; SGD 80,000 - 120,000; Full time

Job summary

A leading technology company in Singapore seeks a skilled professional to handle netlist to GDSII processes and implement high-performance core designs. The ideal candidate must have expertise in EDA, particularly using Synopsys ICC, and possess solid timing closure skills. This role involves complex design tasks at various levels to meet stringent performance specifications.

Responsibilities

• Netlist to GDSII at multiple levels.
• Implement high performance cores and low power designs.
• Perform timing closure with crosstalk considerations.

Skills

Netlist to GDSII

Timing Signoff

Hierarchical partitioning

TCL scripting

PnR tools

Tools

Synopsys ICC

Cadence Innovus

Job description

Responsibilities

• Netlist to GDSII at block level, Subsystem Level and at Full chip.
• Worked on multiple tapeouts on Netlist to GDSII
• Hierarchical partitioning and budgeting of block-level subsystems.
• Implementation of high performance (HP) cores, low power designs
• Node experience upto 7nm, 10nm, 14nm, 28nm.
• Timing Signoff in loop through STA and ECO cycle at block and at interface.
• Block level floor planning, power planning and IR drop analysis.
• Scan chain reordering / Scan Chain repartitioning
• CTS expertise and clock tree constraints creation for meeting specifications
• MMMC optimization at Block and Sub-System Level
• Timing closure with Crosstalk and AOCV / POCV
• TCL scripting to fundamentally understand tool usage.

Mandatory EDA Skills

• PnR tools such as Synopsys ICC/ICC2 and/or Cadence Innovus