Physical Design Engineer

BITMAIN DEVELOPMENT PTE. LTD.; Singapore; On-site; SGD 45,000 - 78,000; Full time

Job summary

BITMAIN DEVELOPMENT PTE. LTD. in Singapore seeks new graduates for an entry-level IC design role.

The position focuses on advanced process digital ASIC/AI/CPU chip design and packaging exploration in a fast-paced technology setting. You will contribute to back-end physical implementation from gate-level netlist to GDSII and assist layout tasks for digital/analog cells, including signoff activities. A Master’s degree or higher is required, and a strong curiosity with quick learning ability is

Qualifications

• Recent graduates or those who graduated within the past year with a master's degree or higher in fields including but not limited to Mathematics, Physics, Electronic Science and Technology, Microelectronics, Information and Communication Engineering, Computer Science and Technology, or Materials Science and Engineering.
• Excellent academic performance, with a strong curiosity, learning ability, and knowledge transfer capability in new areas and related professional fields.
• Understanding of the IC development process, with a certain theoretical foundation in digital circuits, practical skills, and innovation ability.

Responsibilities

• Responsible for the physical design of advanced process digital ASIC/AI/CPU chips, layout design of analog/digital chips, PPAC optimization under advanced processes, fully custom design, and exploration of new technologies in advanced packaging.
• Multiple tasks including but not limited to: back-end physical implementation from gate-level netlist to GDSII, layout design of digital/analog chips, including PR, PV, IR signoff, PPAC optimization, and STA/Spice signoff.

Skills

Curiosity

Learning ability

Knowledge transfer

Education

Master's degree or higher in relevant fields

Job description

Responsibility

1. Responsible for the physical design of advanced process digital ASIC/AI/CPU chips, layout design of analog/digital chips, PPAC optimization under advanced processes, fully custom design, and exploration of new technologies in advanced packaging.
2. Multiple tasks including but not limited to: back-end physical implementation from gate-level netlist to GDSII, layout design of digital/analog chips, including PR, PV, IR signoff, PPAC optimization, and STA/Spice signoff.

Requirement

1. Recent graduates or those who graduated within the past year with a master's degree or higher in fields including but not limited to Mathematics, Physics, Electronic Science and Technology, Microelectronics, Information and Communication Engineering, Computer Science and Technology, or Materials Science and Engineering.
2. Excellent academic performance, with a strong curiosity, learning ability, and knowledge transfer capability in new areas and related professional fields.
3. Understanding of the IC development process, with a certain theoretical foundation in digital circuits, practical skills, and innovation ability.