LPU Chip Architecture Engineer

CANAAN CREATIVE GLOBAL PTE. LTD.; Singapore; On-site; SGD 180,000 - 240,000; Full time

Job summary

CANAAN CREATIVE GLOBAL PTE. LTD. is seeking a PhD-level architect to define and optimize the LPU chip architecture for large model inference. You will collaborate across compiler, hardware design, and architecture teams to create efficient microarchitectures and evaluate performance and power.

You will prototype via FPGA, validate bring-up, and contribute to future design improvements while staying aligned with industry AI accelerator trends and model inference workflows.

Qualifications

• PhD in a relevant field is required.
• Solid understanding of computer architecture and AI accelerator architecture.
• Familiar with inference workflow of large models and memory hierarchy is a plus.
• Experience with AI accelerators, NPUs, GPUs, or related architectures in research or projects.
• Experience with architectural simulation methodologies and performance analysis.
• Strong programming skills (C/C++, Python) and hardware languages (Verilog/SystemVerilog) preferred.
• Good communication and cross-team collaboration skills.

Responsibilities

• Define the overall architecture of LPU chips based on a static dataflow architecture for large model inference.
• Collaborate with compiler engineers to define hardware microarchitecture and co-design strategies before tape-out.
• Build architectural models to evaluate compute performance, memory bandwidth, latency, and power.
• Research inference characteristics of MoE and multimodal models to optimize LPU architecture for AI workloads.
• Participate in front-end chip design, FPGA prototyping, bring-up and validation.
• Investigate and contribute to architecture evaluation and future design improvements.

Skills

Computer architecture

AI accelerator architecture

Static dataflow architecture

Systolic array architecture

Prefill/Decode inference

Verilog/SystemVerilog

C/C++, Python

Education

PhD in Microelectronics / Integrated Circuits / Computer Architecture / Computer Engineering / Electrical Engineering

Tools

FPGA

Chip design

Job description

Responsibilities

1. Define the overall architecture of LPU chips based on a static dataflow architecture, including compute array design and on-chip SRAM memory hierarchy planning, to address latency and data movement challenges in large model inference.


2. Collaborate with compiler engineers to define hardware microarchitecture and enable hardware-software co-design, ensuring efficient scheduling strategies before tape-out.


3. Build architectural models to evaluate compute performance, memory bandwidth, latency, and power consumption, and benchmark LPU architecture against GPU and NPU architectures.


4. Research the inference characteristics of MoE and multimodal foundation models, and continuously optimize the LPU architecture for next-generation AI workloads.


5. Participate in front-end chip design, FPGA prototyping, chip bring-up, and performance validation.


6. Investigate state-of-the-art AI accelerator architectures (e.g. Groq, Etched, Cerebras), and contribute to architecture evaluation and future design improvements.

Qualifications

1. PhD graduate in Microelectronics, Integrated Circuits, Computer Architecture, Computer Engineering, Electrical Engineering, or a related field.


2. Solid understanding of computer architecture, AI accelerator architecture, static dataflow architecture, or systolic array architecture.


3. Familiar with the inference workflow of large language models, including Prefill and Decode stages. Knowledge of memory hierarchy and on-chip SRAM optimization is a plus.


4. Experience through research projects, FPGA implementation, or chip design projects involving AI accelerators, NPUs, GPUs, or related architectures.


5. Familiar with computer architecture modeling, performance analysis, or architectural simulation methodologies.


6. Strong programming skills (e.g. C/C++, Python) and familiarity with hardware design languages (Verilog/SystemVerilog) are preferred.


7. Good communication skills and the ability to collaborate across architecture, compiler, and hardware design teams.