IC & Photonic Layout Engineer for Optical AI silicon

Lumilens Inc.; Singapore; On-site; SGD 70,000 - 110,000; Full time

Job summary

Lumilens builds optical interconnect for AI data centers in Singapore, focusing on silicon photonics and high-speed ICs. You will own layout for electronic ICs (EICs) and photonic ICs (PICs), ensuring routing, impedance control, and parasitic awareness from floorplan to sign-off.

You will work with a senior layout engineer and global design teams, supporting PIC layout when needed and integrating electronic and photonic dies to deliver robust, production-ready parts.

Qualifications

• Diploma, BS, or MS in Electrical or Electronics Engineering, or equivalent hands‑on layout experience.
• 1-3 years in custom analog, RF, or mixed‑signal IC layout, including at least one tapeout you contributed to through to silicon.
• Solid working experience with Cadence Virtuoso, including Layout XL and constraint‑driven flows.
• Parasitic awareness in practice - you understand why a matched pair is drawn the way it is, and which nets on your block deserve the extra care.
• Fundamentals in electromigration and IR drop: current density limits, power routing, and the checks that catch problems.
• Fundamentals in electromagnetics for on‑chip structures - coupling, shielding, and why high‑speed routing is constrained the way it is.
• Physical verification experience: Calibre or PVS DRC/LVS, and parasitic extraction with QRC, StarRC, or equivalent.
• Some scripting for layout automation - SKILL, Python, or both.
• Willingness to overlap with US and India hours during tape out crunch.

Responsibilities

• Own layout for assigned analog and mixed-signal blocks: device placement, matching and symmetry, shielding, guard rings, and routing, from floorplan through to clean sign-off.
• Execute parasitic-aware layout - build to the constraints given by designers, run extraction, and take the results back to them when the layout says something the schematic did not expect.
• Route high-speed signal paths with attention to impedance, coupling, and return paths, and lay out passive and electromagnetic structures under senior direction.
• Run and close DRC, LVS, antenna, and density checks on your blocks, and support electromigration and IR drop analysis.
• Support top-level assembly and chip finishing activities through tape out.
• Support PIC layout as the need arises, including waveguide and curvilinear structures.
• Lay out photonic components and waveguide routing - bends, tapers, couplers, grating and edge couplers, and modulator and photodetector electrodes - from designer-provided geometry, honoring minimum bend radius, waveguide spacing, and phase- and length-matching constraints.
• Run photonics-specific verification: curvilinear DRC against the photonics PDK, waveguide connectivity and port checks, LVS on custom photonic cells, and clean GDS stream-out for tape out.
• Build the scripts and reusable structures that make the layout team faster.

Skills

Parasitic awareness

High-speed layout

Electromagnetic fundamentals

Scripting (SKILL/Python)

Education

Bachelor's degree in Electrical/Electronics Engineering

Tools

Cadence Virtuoso

Layout XL

Calibre/PVS DRC/LVS

QRC/StarRC

Job description

Lumilens builds optical interconnect for AI data centers in Singapore, focusing on silicon photonics and high-speed ICs. You will own layout for electronic ICs (EICs) and photonic ICs (PICs), ensuring routing, impedance control, and parasitic awareness from floorplan to sign-off.

You will work with a senior layout engineer and global design teams, supporting PIC layout when needed and integrating electronic and photonic dies to deliver robust, production-ready parts.