HW System and SoC Architect

Ethos Search Associates Pte Ltd; Singapore; On-site; SGD 180,000 - 260,000; Full time

Job summary

Ambiq in Singapore seeks a Senior SoC Architect to lead architecture for peripheral subsystems like audio, imaging/display, and high-/low-speed interfaces. You’ll shape the silicon architecture across the full lifecycle—from spec to post-silicon validation—balancing power, performance, and integration with RTL, physical design, and software teams.

You will define modes, interfaces, PHY behavior, and driver models across board-to-silicon boundaries, ensuring robust, power-efficient

Qualifications

• Authorship of architectural specs for SoCs/ASICs with RTL implementation
• 8+ years in SoC/ASIC architecture or silicon IP development
• Experience connecting SoC to external world: audio, imaging/display, high-/low-speed links
• Knowledge of board-level electrical constraints, cabling, PHY integration
• Proven track record delivering low-power silicon architectures
• Ability to drive concept through specs, design, and post-silicon validation
• Understanding of low-power mobile/embedded imaging or NN processing
• Strong systems-level thinking and cross-domain trade-off skills
• Able to align geographically distributed teams and build consensus

Responsibilities

• Architecture specifications for the SoC peripheral subsystems: micro-architecture, diagrams, models
• Off-die interface definition including modes, electrical/protocol behavior, integration
• Debug at RTL and gate level with design teams to resolve specification questions
• Collaborate with physical design to ensure robust implementation of specifications
• Perform power and performance trade-off analysis across die, package, board, and software
• IP investigation, assessment, and selection with build-vs-license rationale
• Create integration specifications for system interfaces and external PMU
• Provide post-silicon analysis and support for mass production delivery
• Define use cases and test cases to validate architecture decisions

Skills

Architectural specifications

Systems thinking

Cross-functional collaboration

Power/thermal optimization

Threading hardware/software boundaries

Excellent written/verbal communication

Leadership across distributed teams

RTL familiarity

Debug at RTL/gate level

Education

Bachelor's in Electrical/Computer Engineering or CS

Job description

The work

You will represent the Architecture function in Ambiq's Singapore development office and serve as the primary architectural guide for the site's engineering team.

Your focus is the SoC's peripheral subsystems — audio, imaging and display, and high- and low-speed interfaces — architected for the power budgets of battery-powered wearables and IoT devices. On a sub-threshold SoC, external interfaces frequently dominate the power budget, so decisions that are routine elsewhere (when a link wakes, what stays retained, how data moves without waking the CPU) become first-order architectural problems.

These subsystems live on both sides of the package, and so does this role. Defining them properly requires fluency beyond the pins: cable and connector requirements, board-level electrical constraints, PHY behavior, and the driver model on the far side of the interface. A USB mode definition that ignores cable power delivery or the host driver stack is wrong before tape-out. You will be expected to reason across that whole span — and to deliver it as silicon architecture.

What you'll own

Ordered by how you'll spend your time — the silicon lifecycle runs through all of it.

• Architecture specificationsfor the SoC's peripheral subsystems: micro-architecture definition, flow and sequence diagrams, power and performance models, and pseudocode — the documents RTL design and verification teams implement from


• Off-die interface definition— modes, electrical and protocol behavior, and integration requirements that account for boards, cables, connectors, PHYs, and the software driver model


• Debug at RTL and gate levelwith the design team when implementation raises questions the specification must answer


• Partnership with physical designto ensure robust, optimal implementation of what you specify


• Power and performance trade-off analysisacross full system dataflows — die, package, board, and software — guiding both hardware and software development


• IP investigation, assessment, and selection— build-vs-license recommendations with the analysis to back them


• Integration specificationscovering system interfaces and external power management


• Post-silicon analysisand support for delivery of SoC functionality into mass production


• Use case and test case definitionin support of validation

Who you'll work with

• RTL design and verification teams— the primary consumers of your specifications


• Physical design— implementation feasibility, floorplan, and power-domain implications of architectural choices


• The FPGA team— bringing up critical subsystem and interface features ahead of silicon


• Software architecture— data and control flows, APIs, and hardware abstraction layers


• Marketing, Advanced Development, and the Austin architecture team— technology roadmap and architectural alignment


• Customers, applications engineering, and field teams— key features and competitive positioning

Required

• Authorship of architectural specifications for SoCs, ASICs, or silicon IP — documents that hardware design teams implemented in RTL. This is the core of the role and the first thing we will ask about.


• 8+ years in SoC or ASIC architecture and design, or silicon IP development (hardware implemented in RTL — not firmware or driver development), targeting wearable, IoT, or mobile-class products


• Experience architecting how an SoC connects to the external world — audio (I2S, PDM), imaging and display (MIPI CSI/DSI), and high- and low-speed links (USB, SPI, I2C)


• Working knowledge of each interface on both sides of the package — board-level electrical constraints, cable and connector requirements (e.g., USB power delivery and cabling), PHY integration, and the operating-system driver model — sufficient to define modes and interfaces that hold up in real systems


• Proven experience bringing low‑power silicon architectures to market


• Track record of taking novel solutions from concept through specification, design, and post‑silicon validation


• Working knowledge of low‑power mobile consumer systems, and of embedded imaging or neural network processing


• Strong systems‑level thinking — able to reason across the hardware/software boundary and own trade-offs spanning multiple subsystems


• Able to build consensus and drive architectural alignment across geographically distributed teams


• Excellent written and verbal communication


• BS in Electrical Engineering, Computer Engineering, or Computer Science