Frame Engineering Intern — Pioneering Chip Fabrication

GlobalFoundries; Singapore; On-site; SGD 13,000 - 20,000; Full time

Job summary

GlobalFoundries is seeking a motivated intern to join the Tape out organization as an Intern Frame Engineering in Singapore. The role supports frame design and process improvements, working with global engineers using semiconductor tools in Fabs.

You will engage in continuous process improvement, perform analysis with Failure Mode and Effects, and contribute to reducing risks while gaining hands‑on exposure in a leading semiconductor manufacturing environment.

Qualifications

• Actively pursuing a Bachelor’s degree in Engineering or Physics during the internship.

Responsibilities

• Engage in daily frame engineering operations including frame requirements, layout, and generation for chips across sites.
• Use internally developed and commercial tools to enhance design productivity and generate input files for Fabs and Mask House.
• Make decisions to hold, elevate, promote, or reject tape-out issues in alignment with FAB and Tape-out teams.
• Collaborate with Application, Product, Release, and Design Enablement teams to deliver a best-in-class Customer Tape-out experience.
• Work with FAB and TD teams to improve efficiency, reduce costs and shorten cycle times.
• Suggest process improvements and automation opportunities to boost team productivity.
• Ensure processes are well documented and include mitigation for failure modes.

Skills

Unix shells

Programming/scripting

SKILL Programming

Virtuoso

Cadence Mask Compose

Education

Bachelor's degree in Chemical Engineering, Electrical/Electronic Engineering, Mechanical Engineering or Physics

Tools

Cadence Mask Compose

Virtuoso

Job description

GlobalFoundries is seeking a motivated intern to join the Tape out organization as an Intern Frame Engineering in Singapore. The role supports frame design and process improvements, working with global engineers using semiconductor tools in Fabs.

You will engage in continuous process improvement, perform analysis with Failure Mode and Effects, and contribute to reducing risks while gaining hands‑on exposure in a leading semiconductor manufacturing environment.