Engineer (Semicon, One North)

PERSOL; Singapore; On-site; SGD 54,000 - 89,000; Full time

Job summary

PERSOL is seeking a Custom Layout Engineer in Singapore to support physical implementation of Foundation IP, Analog IP, and RFIC designs. The role covers full-chip layout development, physical verification, and optimization for power, performance, and area (PPA).

12-month contract based at One North; candidate should have 3+ years in layout and strong Cadence/Synopsys tool proficiency. Collaboration across design teams to ensure timely, high-quality layouts.

Qualifications

• 3+ years of experience in custom layout, analog layout, RFIC, or Foundation IP design.
• Hands-on experience with advanced CMOS technologies (FinFET and/or GAA).
• Proficiency in Cadence and/or Synopsys layout and verification tools.
• Strong understanding of DRC, LVS, ERC, ESD, SI/PI, EM/IR, and DFM concepts.
• Bachelor's Degree in Electrical/Electronic Engineering or related discipline.

Responsibilities

• Perform custom layout implementation for IO/ESD, Analog, and RF circuits.
• Handle floorplanning, layout construction, physical verification, and sign-off activities.
• Conduct DRC, LVS, ERC, and other verification checks to ensure design quality.
• Collaborate with design, verification, and cross-functional teams to optimize layouts.
• Support project execution and provide regular status updates to stakeholders.
• Ensure timely delivery of high-quality layouts across multiple technology nodes.

Skills

Analog/Layout experience

RFIC knowledge

DRC/LVS/ERC understanding

Teamwork

Communication

Education

Bachelor's Degree in Electrical/Electronic Engineering

Tools

Cadence tools

Synopsys tools

Job description

We are seeking a Custom Layout Engineer to support the physical implementation of Foundation IP, Analog IP, and RFIC designs across advanced semiconductor process technologies. The role involves full-chip layout development, physical verification, and optimization for power, performance, and area (PPA).

Salary up to $8000
Contract: 12 months
Location: One North

Key Responsibilities:

• Perform custom layout implementation for IO/ESD, Analog, and RF circuits.
• Handle floorplanning, layout construction, physical verification, and sign-off activities.
• Conduct DRC, LVS, ERC, and other verification checks to ensure design quality.
• Collaborate with design, verification, and cross-functional teams to optimize layouts.
• Support project execution and provide regular status updates to stakeholders.
• Ensure timely delivery of high-quality layouts across multiple technology nodes.

Requirements:

• Bachelor's Degree in Electrical/Electronic Engineering or related discipline.
• 3+ years of experience in custom layout, analog layout, RFIC, or Foundation IP design.
• Hands-on experience with advanced CMOS technologies (FinFET and/or GAA).
• Proficiency in Cadence and/or Synopsys layout and verification tools.
• Strong understanding of DRC, LVS, ERC, ESD, SI/PI, EM/IR, and DFM concepts.
• Good communication and teamwork skills.

Preferred

• Experience with IO/ESD layout development.
• Familiarity with advanced foundry design rules and backend implementation flows.